From WikiChip
Difference between revisions of "pezy/pezy-scx/pezy-sc2"
Line 30: | Line 30: | ||
|type=DDR4-2666 | |type=DDR4-2666 | ||
|ecc=Yes | |ecc=Yes | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
}} | }} | ||
Revision as of 01:04, 1 November 2017
Template:mpu PEZY-SC2 (PEZY Super Computer 2) is third generation many-core microprocessor developed by PEZY released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor.
PEZY-SC2 operates at 1 GHz and consume around 200 W while delivering performance in the order of 16.4 TFLOPS (HP), 8.2 TFLOPS (SP), and 4.1 TFLOPS (DP). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's 16 nm process.
Memory controller
![]() |
Integrated Memory Controller
|
|||
|
![]() |
Integrated Memory Controller
|
|||||||||
|
Expansions
![]() |
Expansion Options
|
|||||||||||
|
Facts about "PEZY-SC2 - PEZY"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-SC2 - PEZY#io + |
has ecc memory support | true + and false + |
max memory bandwidth | 1,907.712 GiB/s (1,953,497.088 MiB/s, 2,048.39 GB/s, 2,048,390.163 MB/s, 1.863 TiB/s, 2.048 TB/s) + |
max memory channels | 4 + |
max pcie lanes | 32 + |
supported memory type | DDR4-2666 + |