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Difference between revisions of "freescale/qoriq/p1011"
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− | '''QorIQ P1011''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 800 MHz and supports 32-bit | + | '''QorIQ P1011''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 800 MHz and supports 32-bit DDR3-800 memory. |
== Cache == | == Cache == |
Revision as of 22:48, 24 October 2017
Template:mpu QorIQ P1011 is a 32-bit embedded POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 800 MHz and supports 32-bit DDR3-800 memory.
Cache
- Main article: e500 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
- 3x 10/100/1000 Eithernet with 2x SGMII
- 2x PCIe 1.0a controllers with 2 SerDes
- 2x USB 2.0
- SD/MMC
- SPI
- 2x I2C
- UART
- SEC 3.1 Security Acceleration
Block Diagram
Documents
Facts about "QorIQ P1011 - Freescale"
has ecc memory support | true + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
max memory bandwidth | 2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR3-800 + |