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Difference between revisions of "hisilicon/k3/k3v1"
(Created page with "{{hisilicon title|K3V1}} {{mpu}} '''K3V1''' is a {{arch|32}} performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single core...") |
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{{hisilicon title|K3V1}} | {{hisilicon title|K3V1}} | ||
| − | {{mpu}} | + | {{mpu |
| + | |name=K3V1 | ||
| + | |no image=Yes | ||
| + | |designer=HiSilicon | ||
| + | |manufacturer=TSMC | ||
| + | |model number=K3V1 | ||
| + | |part number=Hi3611 | ||
| + | |market=Mobile | ||
| + | |first announced=June, 2008 | ||
| + | |first launched=June, 2008 | ||
| + | |family=K3 | ||
| + | |frequency=460 | ||
| + | |isa=ARMv5 | ||
| + | |isa family=ARM | ||
| + | |microarch=ARM9 | ||
| + | |core name=ARM926EJ-S | ||
| + | |process=0.18 µm | ||
| + | |transistors=200,000,000 | ||
| + | |technology=CMOS | ||
| + | |word size=32 bit | ||
| + | |core count=1 | ||
| + | |thread count=1 | ||
| + | |max cpus=1 | ||
| + | |package module 1={{packages/hisilicon/tfbga-460}} | ||
| + | }} | ||
'''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory. | '''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory. | ||
Revision as of 22:57, 5 September 2017
Template:mpu K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
Facts about "K3V1 - HiSilicon"
| has ecc memory support | false + |
| l1$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| max memory channels | 1 + |
| supported memory type | DDR + |