Semiconductor & Computer Engineering
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Difference between revisions of "intel/pentium (2009)/b980"
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== Cache == | == Cache == | ||
| + | {{main|intel/microarchitectures/sandy_bridge#Memory_Hierarchy|l1=Sandy Bridge § Cache}} | ||
| + | {{cache size | ||
| + | |l1 cache=128 KiB | ||
| + | |l1i cache=64 KiB | ||
| + | |l1i break=2x32 KiB | ||
| + | |l1i desc=8-way set associative | ||
| + | |l1d cache=64 KiB | ||
| + | |l1d break=2x32 KiB | ||
| + | |l1d desc=8-way set associative | ||
| + | |l1d policy=write-back | ||
| + | |l2 cache=512 KiB | ||
| + | |l2 break=2x256 KiB | ||
| + | |l2 desc=8-way set associative | ||
| + | |l2 policy=write-back | ||
| + | |l3 cache=2 MiB | ||
| + | |l3 break=2x1 MiB | ||
| + | |l3 desc=8-way set associative | ||
| + | |l3 policy=write-back | ||
| + | }} | ||
== Memory controller == | == Memory controller == | ||
Revision as of 01:26, 22 August 2017
Cache
- Main article: Sandy Bridge § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Expansions
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Expansion Options |
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Graphics
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Pentium B980 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Pentium B980 - Intel#pcie + |