Semiconductor & Computer Engineering
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Difference between revisions of "intel/pentium (2009)/907"
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|l2 policy=write-back | |l2 policy=write-back | ||
|l3 cache=2 MiB | |l3 cache=2 MiB | ||
| − | |l3 break= | + | |l3 break=2x1 MiB |
|l3 desc=8-way set associative | |l3 desc=8-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
Revision as of 01:24, 22 August 2017
Cache
- Main article: Sandy Bridge § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Expansions
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Expansion Options |
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Graphics
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Pentium 907 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Pentium 907 - Intel#pcie + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 8-way set associative + |
| l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |