From WikiChip
Difference between revisions of "intel/core i5/i5-8350u"
< intel‎ | core i5

Line 45: Line 45:
 
|package module 1={{packages/intel/fcbga-1356}}
 
|package module 1={{packages/intel/fcbga-1356}}
 
}}
 
}}
−
'''Core i5-8350U''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile microprocessor set to be introduced by [[Intel]] in late [[2017]]. This chip, which is based on the {{intel|Coffee Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm++ process]]. The i5-8350U operates at ? GHz with a TDP of 15 W supporting a {{intel|Turbo Boost}} frequency of ? GHz. The processor supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory.
+
'''Core i5-8350U''' is a {{arch|64}} [[quad-core]] performance [[x86]] mobile microprocessor introduced by [[Intel]] in mid-[[2017]]. This processor, which is based on an enhanced version of the {{intel|Kaby Lake|l=arch}} microarchitecture, is manufactured on Intel's 2nd generation enhanced [[14 nm process|14nm+ process]]. The i5-8350U operates at 1.7 GHz with a TDP of 15 W and {{intel|Turbo Boost}} frequency of up to 3.6 GHz. This MPU supports up to 32 GiB of dual-channel DDR4-2400 memory.
−
 
 
−
 
 
−
{{unknown features}}
 
−
 
 
  
 
== Cache ==
 
== Cache ==

Revision as of 03:38, 21 August 2017

Template:mpu Core i5-8350U is a 64-bit quad-core performance x86 mobile microprocessor introduced by Intel in mid-2017. This processor, which is based on an enhanced version of the Kaby Lake microarchitecture, is manufactured on Intel's 2nd generation enhanced 14nm+ process. The i5-8350U operates at 1.7 GHz with a TDP of 15 W and Turbo Boost frequency of up to 3.6 GHz. This MPU supports up to 32 GiB of dual-channel DDR4-2400 memory.

Cache

Main article: Coffee Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  4x1.5 MiB12-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866, DDR3L-1600, DDR4-2133
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes12
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics

New text document.svg This section is empty; you can help add the missing info by editing this page.

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i5/i5-8350u&oldid=61766"
Facts about "Core i5-8350U - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core i5-8350U - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel my wifi technology supporttrue +
has intel secure key technologytrue +
has intel smart response technology supporttrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel turbo boost technology 2 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description12-way set associative +
l3$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes12 +
supported memory typeLPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +