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Difference between revisions of "qualcomm/microarchitectures/falkor"
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== Process Technology == | == Process Technology == | ||
Falkor-based chips are manufactured on [[TSMC]]'s [[10 nm process]]. | Falkor-based chips are manufactured on [[TSMC]]'s [[10 nm process]]. | ||
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+ | == Architecture == | ||
+ | {{empty section}} | ||
+ | === Block Diagram === | ||
+ | {{empty section}} |
Revision as of 15:15, 20 August 2017
Edit Values | |
Falkor µarch | |
General Info | |
Arch Type | CPU |
Designer | Qualcomm |
Manufacturer | TSMC |
Introduction | 2017 |
Process | 10 nm |
Core Configs | 42 |
Pipeline | |
Type | Superscalar, Superpipeline |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 10-15 |
Decode | 4-way |
Instructions | |
ISA | ARMv8 |
Cache | |
L1I Cache | 64 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
Falkor is an ARM microarchitecture being designed by Qualcomm for the server market. Falkor-based microprocessors will be manufactured on a 10 nm process and sold under the Centriq brand.
Process Technology
Falkor-based chips are manufactured on TSMC's 10 nm process.
Architecture
This section is empty; you can help add the missing info by editing this page. |
Block Diagram
This section is empty; you can help add the missing info by editing this page. |
Facts about "Falkor - Microarchitectures - Qualcomm"
codename | Falkor + |
core count | 42 + |
designer | Qualcomm + |
first launched | 2017 + |
full page name | qualcomm/microarchitectures/falkor + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Falkor + |
pipeline stages (max) | 15 + |
pipeline stages (min) | 10 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |