From WikiChip
Difference between revisions of "intel/celeron/817"
< intel‎ | celeron

(→‎Expansions)
(→‎Cache)
Line 55: Line 55:
  
 
== Cache ==
 
== Cache ==
 +
{{main|intel/microarchitectures/sandy_bridge#Memory_Hierarchy|l1=Sandy Bridge § Cache}}
 +
{{cache size
 +
|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=2x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=64 KiB
 +
|l1d break=2x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=512 KiB
 +
|l2 break=2x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=2 MiB
 +
|l3 break=2x1 MiB
 +
|l3 desc=8-way set associative
 +
|l3 policy=write-back
 +
}}
  
 
== Memory controller ==
 
== Memory controller ==

Revision as of 21:10, 19 August 2017

Template:mpu

Cache

Main article: Sandy Bridge § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB8-way set associativewrite-back
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB8-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1333, DDR3-1066
Supports ECCNo
Max Mem16 GiB
Controllers1
Channels2
Max Bandwidth19.87 GiB/s
20,346.88 MiB/s
21.335 GB/s
21,335.25 MB/s
0.0194 TiB/s
0.0213 TB/s
Bandwidth
Single 9.93 GiB/s
Double 19.87 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 2.0
Max Lanes: 16
Configuration: 1x16, 2x8, 1x8+2x4


Graphics

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/817&oldid=59030"
Facts about "Celeron 817 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron 817 - Intel#package + and Celeron 817 - Intel#pcie +
base frequency1,600 MHz (1.6 GHz, 1,600,000 kHz) +
bus links4 +
bus rate5,000 MT/s (5 GT/s, 5,000,000 kT/s) +
bus typeDMI 2.0 +
chipsetCougar Point +
clock multiplier16 +
core count2 +
core family6 +
core model42 +
core nameSandy Bridge M +
core steppingJ1 + and Q0 +
core voltage (max)1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)0.3 V (3 dV, 30 cV, 300 mV) +
cpuid0x206A7 +
designerIntel +
device id0x0106 +
die area131 mm² (0.203 in², 1.31 cm², 131,000,000 µm²) +
familyCeleron +
first announced2012 +
first launched2012 +
full page nameintel/celeron/817 +
has ecc memory supportfalse +
has featureIntel VT-x +, Flex Memory Access + and Enhanced SpeedStep Technology +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
instance ofmicroprocessor +
integrated gpuHD Graphics (Sandy Bridge) +
integrated gpu base frequency350 MHz (0.35 GHz, 350,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units6 +
integrated gpu max frequency800 MHz (0.8 GHz, 800,000 KHz) +
isax86-64 +
isa familyx86 +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description8-way set associative +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate2012 +
manufacturerIntel +
market segmentMobile +
max cpu count1 +
max junction temperature373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) +
max memory channels2 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureSandy Bridge +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number817 +
nameCeleron 817 +
packageFCBGA-1023 +
part numberAV8062701079800 +, AV8062701079801 +, AV8062701079802 + and AV8062701345700 +
platformSandy Bridge M +
power dissipation (idle)2.3 W (2,300 mW, 0.00308 hp, 0.0023 kW) +
process32 nm (0.032 μm, 3.2e-5 mm) +
s-specSR07H +, SR0EF +, SR0PX + and SR0VM +
series800 +
smp max ways1 +
supported memory typeDDR3-1333 + and DDR3-1066 +
tdp17 W (17,000 mW, 0.0228 hp, 0.017 kW) +
technologyCMOS +
thread count2 +
transistor count504,000,000 +
word size64 bit (8 octets, 16 nibbles) +