From WikiChip
Difference between revisions of "mips/prid register"

(Thanks you, post it great)
Line 1: Line 1:
The '''Processor ID''' ('''PRId''') is a read-only, special-purpose register found in the [[MIPS32]] and [[MIPS64]] ISAs that can be queried to identify the [[MIPS]] CPU. The Processor ID should be unique for each instruction set or CPU control register change. The PRId is the 15th register in [[Coprocessor 0 - MIPS|Coprocessor 0]].
+
abc
 
 
== Register layout ==
 
The PRId is the 15th register in [[Coprocessor 0 - MIPS|Coprocessor 0]]. It contains company options, company ID, CPU ID, and revision ID.
 
{| class="wikitable"
 
|-
 
| <span style="float: left">31</span><span style="float: right">24</span> || <span style="float: left">23</span><span style="float: right">16</span> || <span style="float: left">15</span><span style="float: right">8</span> || <span style="float: left">7</span><span style="float: right">0</span>
 
|-
 
| align="center" style="width: 150px;" | Company Options ||  align="center"  style="width: 150px;" | Company ID ||  align="center"  style="width: 150px;" | CPU ID ||  align="center"  style="width: 150px;" | Revision
 
|}
 
 
 
=== Company Options ===
 
The Company Options field is the most significant byte of the RPId register. The company options field depends on the manufacturer and the exact model being used. Consult your CPU manual for more information.
 
 
 
=== Company ID ===
 
The Company ID field is located at bits 16 through 23. Because the company ID is a relatively new addition, legacy processors have it defined as 0. The linux kernel defines the following values:<ref>[https://github.com/torvalds/linux/blob/master/arch/mips/include/asm/cpu.h GitHub linux/arch/mips/include/asm/cpu.h]</ref>
 
 
 
{| class="wikitable sortable"
 
|-
 
! Company ID !! Company
 
|-
 
| 0x000000 || Legacy
 
|-
 
| 0x010000 || MIPS
 
|-
 
| 0x020000 || Broadcom
 
|-
 
| 0x030000 || Alchemy
 
|-
 
| 0x040000 || Sibyte
 
|-
 
| 0x050000 || Sandcraft
 
|-
 
| 0x060000 || NXP
 
|-
 
| 0x070000 || Toshiba
 
|-
 
| 0x080000 || LSI
 
|-
 
| 0x0b0000 || Lexra
 
|-
 
| 0x0c0000 || Netlogic
 
|-
 
| 0x0d0000 || Cavium
 
|-
 
| 0xd00000 || Ingenic
 
|}
 
 
 
=== CPU ID ===
 
==== Legacy ====
 
{| class="wikitable sortable"
 
|-
 
! CPU ID !! CPU
 
|-
 
| 0x0100 || R2000
 
|-
 
| 0x0100 || AU1 Rev1
 
|-
 
| 0x0200 || AU2 Rev2
 
|-
 
| 0x0200 || R3000
 
|-
 
| 0x0300 || R6000
 
|-
 
| 0x0400 || R4000
 
|-
 
| 0x0600 || R6000A
 
|-
 
| 0x0900 || R10000
 
|-
 
| 0x0b00 || R4300
 
|-
 
| 0x0c00 || VR41XX
 
|-
 
| 0x0e00 || R12000
 
|-
 
| 0x0f00 || R14000
 
|-
 
| 0x1000 || R8000
 
|-
 
| 0x1200 || PR4450
 
|-
 
| 0x2000 || R4600
 
|-
 
| 0x2100 || R4700
 
|-
 
| 0x2200 || TX39
 
|-
 
| 0x2200 || R4640
 
|-
 
| 0x2200 || R4650
 
|-
 
| 0x2300 || R5000
 
|-
 
| 0x2d00 || TX49
 
|-
 
| 0x2400 || SONIC
 
|-
 
| 0x2500 || MAGIC
 
|-
 
| 0x2700 || RM7000
 
|-
 
| 0x2800 || NEVADA (RM5260?)
 
|-
 
| 0x3400 || RM9000
 
|-
 
| 0x4200 || LOONGSON1
 
|-
 
| 0x5400 || R5432
 
|-
 
| 0x5500 || R5500
 
|-
 
| 0x6300 || LOONGSON2
 
|-
 
| 0xff00 || Unknown
 
|}
 
 
 
==== MIPS ====
 
{| class="wikitable sortable"
 
|-
 
! CPU ID !! CPU
 
|-
 
| 0x8000 || 4KC
 
|-
 
| 0x8100 || 5KC
 
|-
 
| 0x8200 || 20KC
 
|-
 
| 0x8400 || 4KEC
 
|-
 
| 0x8600 || 4KSC
 
|-
 
| 0x8800 || 25KF
 
|-
 
| 0x8900 || 5KE
 
|-
 
| 0x9000 || 4KECR2
 
|-
 
| 0x9100 || 4KEMPR2
 
|-
 
| 0x9200 || 4KSD
 
|-
 
| 0x9300 || 24K
 
|-
 
| 0x9500 || 34K
 
|-
 
| 0x9600 || 24KE
 
|-
 
| 0x9700 || 74K
 
|-
 
| 0x9900 || 1004K
 
|-
 
| 0x9a00 || 1074K
 
|-
 
| 0x9c00 || M14KC
 
|-
 
| 0x9e00 || M14KEC
 
|}
 
==== Sibyte ====
 
{| class="wikitable sortable"
 
|-
 
! CPU ID !! CPU
 
|-
 
| 0x0100 || SB1
 
|-
 
| 0x1100 || SB1A
 
|}
 
 
 
==== Sandcraft ====
 
{| class="wikitable sortable"
 
|-
 
! CPU ID !! CPU
 
|-
 
| 0x0400 || SR71000
 
|}
 
==== Broadcom ====
 
{| class="wikitable sortable"
 
|-
 
! CPU ID !! CPU
 
|-
 
| 0x4000 || BMIPS32_REV4
 
|-
 
| 0x8000 || BMIPS32_REV8
 
|-
 
| 0x9000 || BMIPS3300
 
|-
 
| 0x9100 || BMIPS3300_ALT
 
|-
 
| 0x0000 || BMIPS3300_BUG
 
|-
 
| 0xa000 || BMIPS43XX
 
|-
 
| 0x5a00 || BMIPS5000
 
|}
 
 
 
==== Cavium ====
 
{| class="wikitable sortable"
 
|-
 
! CPU ID !! CPU
 
|-
 
| 0x0000 || CAVIUM_CN38XX
 
|-
 
| 0x0100 || CAVIUM_CN31XX
 
|-
 
| 0x0200 || CAVIUM_CN30XX
 
|-
 
| 0x0300 || CAVIUM_CN58XX
 
|-
 
| 0x0400 || CAVIUM_CN56XX
 
|-
 
| 0x0600 || CAVIUM_CN50XX
 
|-
 
| 0x0700 || CAVIUM_CN52XX
 
|-
 
| 0x9000 || CAVIUM_CN63XX
 
|-
 
| 0x9100 || CAVIUM_CN68XX
 
|-
 
| 0x9200 || CAVIUM_CN66XX
 
|-
 
| 0x9300 || CAVIUM_CN61XX
 
|-
 
| 0x9400 || CAVIUM_CNF71XX
 
|-
 
| 0x9500 || CAVIUM_CN78XX
 
|-
 
| 0x9600 || CAVIUM_CN70XX
 
|}
 
 
 
==== Ingenic ====
 
{| class="wikitable sortable"
 
|-
 
! CPU ID !! CPU
 
|-
 
| 0x0200 || JZRISC
 
|}
 
 
 
==== Netlogic ====
 
{| class="wikitable sortable"
 
|-
 
! CPU ID !! CPU
 
|-
 
| 0x0000 || NETLOGIC_XLR732
 
|-
 
| 0x0200 || NETLOGIC_XLR716
 
|-
 
| 0x0900 || NETLOGIC_XLR532
 
|-
 
| 0x0600 || NETLOGIC_XLR308
 
|-
 
| 0x0800 || NETLOGIC_XLR532C
 
|-
 
| 0x0a00 || NETLOGIC_XLR516C
 
|-
 
| 0x0b00 || NETLOGIC_XLR508C
 
|-
 
| 0x0f00 || NETLOGIC_XLR308C
 
|-
 
| 0x8000 || NETLOGIC_XLS608
 
|-
 
| 0x8800 || NETLOGIC_XLS408
 
|-
 
| 0x8c00 || NETLOGIC_XLS404
 
|-
 
| 0x8e00 || NETLOGIC_XLS208
 
|-
 
| 0x8f00 || NETLOGIC_XLS204
 
|-
 
| 0xce00 || NETLOGIC_XLS108
 
|-
 
| 0xcf00 || NETLOGIC_XLS104
 
|-
 
| 0x4000 || NETLOGIC_XLS616B
 
|-
 
| 0x4a00 || NETLOGIC_XLS608B
 
|-
 
| 0x4400 || NETLOGIC_XLS416B
 
|-
 
| 0x4c00 || NETLOGIC_XLS412B
 
|-
 
| 0x4e00 || NETLOGIC_XLS408B
 
|-
 
| 0x4f00 || NETLOGIC_XLS404B
 
|-
 
| 0x8000 || NETLOGIC_AU13XX
 
|-
 
| 0x1000 || NETLOGIC_XLP8XX
 
|-
 
| 0x1100 || NETLOGIC_XLP3XX
 
|-
 
| 0x1200 || NETLOGIC_XLP2XX
 
|}
 
=== Revision ===
 
The revision is a manufacturer dependent value which can be used to track silicon revisions.
 
 
 
== References ==
 
{{reflist|30em}}
 
 
 
[[Category:MIPS]]
 
[[Category:MIPS32]]
 
[[Category:MIPS register]]
 

Revision as of 01:39, 25 July 2014

abc