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Difference between revisions of "intel/atom/c3508"
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| − | '''Atom C3508''' is a {{arch|64}} [[quad-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3508, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 1.6 GHz with a [[TDP]] of 11.25 W. The C3508 supports up to a dual-channel of 256 GiB of DDR4-1866 [[ECC]] memory. | + | '''Atom C3508''' is a {{arch|64}} [[quad-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3508, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 1.6 GHz with a [[TDP]] of 11.25 W. The C3508 supports up to a dual-channel of 256 GiB of DDR4-1866 [[ECC]] memory. This model is part of {{intel|Denverton|l=core}}'s [[part of::Internet of Things and eTEMP SKUs]] which come with integrated {{intel|QuickAssist Technology}} and support extended ambient operating temperature (-40 °C to 85 °C). |
== Cache == | == Cache == | ||
Revision as of 06:25, 16 August 2017
Template:mpu Atom C3508 is a 64-bit quad-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3508, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 1.6 GHz with a TDP of 11.25 W. The C3508 supports up to a dual-channel of 256 GiB of DDR4-1866 ECC memory. This model is part of Denverton's Internet of Things and eTEMP SKUs which come with integrated QuickAssist Technology and support extended ambient operating temperature (-40 °C to 85 °C).
Cache
- Main article: Goldmont § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Atom C3508 - Intel"
| has ecc memory support | true + |
| l1$ size | 224 KiB (229,376 B, 0.219 MiB) + |
| l1d$ description | 6-way set associative + |
| l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| max memory bandwidth | 27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
| max memory channels | 2 + |
| part of | Internet of Things and eTEMP SKUs + |
| supported memory type | DDR3L-1600 + and DDR4-1866 + |