Semiconductor & Computer Engineering
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Difference between revisions of "intel/atom/c3750"
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Revision as of 22:23, 15 August 2017
Template:mpu Atom C3750 is a 64-bit octa-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3750, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2.2 GHz with a TDP of 21 W and a turbo boost frequency of up to 2.4 GHz. The C3750 supports up to a dual-channel of 256 GiB of DDR4-2133 ECC memory.
Cache
- Main article: Goldmont § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Atom C3750 - Intel"
| has ecc memory support | false + |
| l1$ size | 448 KiB (458,752 B, 0.438 MiB) + |
| l1d$ description | 6-way set associative + |
| l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |