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Difference between revisions of "renesas/r-car/h3 (sip)"
< renesas‎ | r-car

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{{renesas title|R-Car H3 (SiP)}}
 
{{renesas title|R-Car H3 (SiP)}}
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{{mpu}}
+
{{mpu
 +
|name=R-Car H3 (SiP)
 +
|image=r-car h3 (sip).png
 +
|image size=125px
 +
|designer=Renesas
 +
|designer 2=ARM Holdings
 +
|manufacturer=TSMC
 +
|model number=H3 (SiP)
 +
|part number=R8J77950
 +
|market=Embedded
 +
|first announced=December 2, 2015
 +
|first launched=March, 2018
 +
|family=R-Car
 +
|series=3rd Gen
 +
|isa=ARMv8
 +
|isa family=ARM
 +
|microarch=Cortex-A53
 +
|microarch 2=Cortex-A57
 +
|microarch 3=Cortex-R7
 +
|core name=Cortex-A53
 +
|core name 2=Cortex-A57
 +
|core name 3=Cortex-R7
 +
|process=16 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=9
 +
|thread count=9
 +
|max cpus=1
 +
|v core=0.8 V
 +
|v io=3.3 V
 +
|package module 1={{packages/renesas/fcbga-1255}}
 +
}}
 
'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.
 
'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.
  
 
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package.
 
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package.

Revision as of 03:13, 23 July 2017

Template:mpu R-Car H3 is a 64-bit nona-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The H3 incorporates four Cortex-A57 cores, four Cortex-A53 cores, and a single Cortex-R7 core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.

This model is an SiP variant of the H3 which include the DDR memory on-package.

Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/h3_(sip)&oldid=56036"
Facts about "R-Car H3 (SiP) - Renesas"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car H3 (SiP) - Renesas#package +
core count9 +
core nameCortex-A53 +, Cortex-A57 + and Cortex-R7 +
core voltage0.8 V (8 dV, 80 cV, 800 mV) +
designerRenesas + and ARM Holdings +
die area111.36 mm² (0.173 in², 1.114 cm², 111,360,000 µm²) +
die length12.94 mm (1.294 cm, 0.509 in, 12,940 µm) +
die width8.61 mm (0.861 cm, 0.339 in, 8,610 µm) +
familyR-Car +
first announcedDecember 2, 2015 +
first launchedMarch 2018 +
full page namerenesas/r-car/h3 (sip) +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR GX6650 +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ size288 KiB (294,912 B, 0.281 MiB) +
l1i$ size352 KiB (360,448 B, 0.344 MiB) +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
ldateMarch 2018 +
main imageFile:r-car h3 (sip).png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory bandwidth47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) +
max memory channels4 +
microarchitectureCortex-A53 +, Cortex-A57 + and Cortex-R7 +
model numberH3 (SiP) +
nameR-Car H3 (SiP) +
packageFCBGA-1255 +
part numberR8J77950 +
process16 nm (0.016 μm, 1.6e-5 mm) +
series3rd Gen +
smp max ways1 +
supported memory typeLPDDR4-3200 +
technologyCMOS +
thread count9 +
word size64 bit (8 octets, 16 nibbles) +