From WikiChip
Difference between revisions of "renesas/r-car/l1"
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* '''Note:''' It's unknown if this model was ever actually released. | * '''Note:''' It's unknown if this model was ever actually released. | ||
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== Cache == | == Cache == |
Revision as of 12:56, 21 July 2017
Template:mpu R-Car L1 is a performance embedded SoC for the automotive industry designed by Renesas. The L1 features a single Cortex-A9 core operating at 400 MHz. This chip incorporates Imagination's PowerVR SGX531 GPU. This SoC supports up to 1 GiB of DDR3-1066 memory.
- Note: It's unknown if this model was ever actually released.
Contents
Cache
- Main article: Cortex-A9 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Graphics
Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Facts about "R-Car L1 - Renesas"
has ecc memory support | false + |
integrated gpu | PowerVR SGX531 + |
integrated gpu designer | Imagination Technologies + |
integrated gpu execution units | 1 + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
max memory bandwidth | 1.99 GiB/s (2,037.76 MiB/s, 2.137 GB/s, 2,136.746 MB/s, 0.00194 TiB/s, 0.00214 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR3-1066 + and DDR2-533 + |