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Difference between revisions of "renesas/r-car/e1"
< renesas‎ | r-car

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|v io=3.3 V
 
|v io=3.3 V
 
|package module 1={{packages/renesas/fcbga-429}}
 
|package module 1={{packages/renesas/fcbga-429}}
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}}
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'''R-Car E1''' is an entry-level performance embedded SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The E1 features a single {{armh|Cortex-A9|l=arch}} core operating at 533 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX531}} [[GPU]] operating at 177 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.
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== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
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{{cache size
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|l1 cache=64 KiB
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|l1i cache=32 KiB
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|l1i break=1x32 KiB
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|l1i desc=4-way set associative
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|l1d cache=32 KiB
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|l1d break=1x32 KiB
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|l1d desc=4-way set associative
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR3-1066
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|type 2=DDR2-533
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|ecc=No
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|max mem=1 GiB
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|controllers=1
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|channels=1
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|width=32 bit
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|max bandwidth=1.99 GiB/s
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|bandwidth schan=1.99 GiB/s
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}}
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== Expansions ==
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{{expansions
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| usb revision      = 2.0
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| usb ports          = 2
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| usb rate          = 480 Mbps
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| uart              = Yes
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| uart ports        = 8
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| sata revision      = 3.0
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| sata ports        = 1
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| i2c                = Yes
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| i2c ports          = 4
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| gp io              = Yes
 +
| jtag              = Yes
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}}
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* MLB (MOST150) 6-Pin I/F
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* 2 x CAN 32 Message Buffers
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* MMC
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* 3 x SD
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== Graphics ==
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{{integrated graphics
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| gpu                = PowerVR SGX531
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| designer            = Imagination Technologies
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| execution units    = 1
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| max displays        = 2
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| frequency          = 177 MHz
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| opengl es ver      = 2.0
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}}
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== Features ==
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{{arm features
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|thumb=No
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|thumb2=Yes
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|thumbee=Yes
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|vfpv1=No
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|vfpv2=No
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|vfpv3=Yes
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=No
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
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|jazelle=Yes
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|wmmx=No
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|wmmx2=No
 
}}
 
}}

Revision as of 12:00, 21 July 2017

Template:mpu R-Car E1 is an entry-level performance embedded SoC for the automotive industry designed by Renesas and introduced in 2011. The E1 features a single Cortex-A9 core operating at 533 MHz. This chip incorporates Imagination's PowerVR SGX531 GPU operating at 177 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB4-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-533
Supports ECCNo
Max Mem1 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth1.99 GiB/s
2,037.76 MiB/s
2.137 GB/s
2,136.746 MB/s
0.00194 TiB/s
0.00214 TB/s
Bandwidth
Single 1.99 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports2
Rate480 Mbps
UART
Ports8
SATA
Revision3.0
Ports1
I²C
Ports4
GP I/OYes
JTAGYes
  • MLB (MOST150) 6-Pin I/F
  • 2 x CAN 32 Message Buffers
  • MMC
  • 3 x SD

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX531
DesignerImagination Technologies
Execution Units1Max Displays2
Frequency177 MHz
0.177 GHz
177,000 KHz
Standards
OpenGL ES2.0

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv3Vector Floating Point (VFP) v3 Extension
NEONAdvanced SIMD extension
JazelleDirect Bytecode eXecution
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/e1&oldid=55674"
Facts about "R-Car E1 - Renesas"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car E1 - Renesas#package +
base frequency533 MHz (0.533 GHz, 533,000 kHz) +
core count1 +
core nameCortex-A9 +
core voltage1.1 V (11 dV, 110 cV, 1,100 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedAugust 25, 2011 +
first launchedJune 2012 +
full page namerenesas/r-car/e1 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX531 +
integrated gpu base frequency177 MHz (0.177 GHz, 177,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units1 +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv7 +
isa familyARM +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description4-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description4-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
ldateJune 2012 +
main imageFile:r-car e1.jpg +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
max memory bandwidth1.99 GiB/s (2,037.76 MiB/s, 2.137 GB/s, 2,136.746 MB/s, 0.00194 TiB/s, 0.00214 TB/s) +
max memory channels1 +
microarchitectureCortex-A9 +
model numberE1 +
nameR-Car E1 +
packageFCBGA-429 +
part numberμPD35004 +
process40 nm (0.04 μm, 4.0e-5 mm) +
release price$ 30.00 (€ 27.00, £ 24.30, ¥ 3,099.90) +
series1st Gen +
smp max ways1 +
supported memory typeDDR3-1066 + and DDR2-533 +
technologyCMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +