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(Intel {{intel|Skylake SP|l=core}} 4-way SMP 2 UPI links. My own drawing.)
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Revision as of 03:53, 14 July 2017

Summary

Intel Skylake SP 4-way SMP 2 UPI links. My own drawing.

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Date/TimeThumbnailDimensionsUserComment
current23:25, 14 July 2017Thumbnail for version as of 23:25, 14 July 20171,389 × 714 (436 KB)At32Hz (talk | contribs)corrected mems more accurately
03:53, 14 July 2017Thumbnail for version as of 03:53, 14 July 20171,164 × 714 (278 KB)At32Hz (talk | contribs)Intel {{intel|Skylake SP|l=core}} 4-way SMP 2 UPI links. My own drawing.
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