Difference between revisions of "intel/xeon gold/5117"

Revision as of 13:23, 11 July 2017

Template:mpu Xeon Gold 5117 is a 64-bit x86 high-performance server tetradeca-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 5117 operates at 2 GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

896 KiB

917,504 B
0.875 MiB

L1I$	448 KiB 458,752 B 0.438 MiB	14x32 KiB	8-way set associative
L1D$	448 KiB 458,752 B 0.438 MiB	28x32 KiB	8-way set associative	write-back

L2$

14 MiB

14,336 KiB
14,680,064 B
0.0137 GiB

		14x1 MiB	16-way set associative	write-back

L3$

19.25 MiB

19,712 KiB
20,185,088 B
0.0188 GiB

		14x1.375 MiB	11-way set associative	write-back

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Controllers	1
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
EIST	Enhanced SpeedStep Technology
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
MPX	Memory Protection Extensions
SMEP	OS Guard Technology

@@ Line 100: / Line 100: @@
 |avx=Yes
 |avx2=Yes
-|avx512=Yes
 |abm=Yes
 |tbm=No

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5117 - Intel#io +
base frequency	2,000 MHz (2 GHz, 2,000,000 kHz) +
chipset	Lewisburg +
clock multiplier	20 +
core count	14 +
core family	6 +
core name	Skylake SP +
cpuid	0x50654 +
designer	Intel +
family	Xeon Gold +
first announced	July 11, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon gold/5117 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	896 KiB (917,504 B, 0.875 MiB) +
l1d$ description	8-way set associative +
l1d$ size	448 KiB (458,752 B, 0.438 MiB) +
l1i$ description	8-way set associative +
l1i$ size	448 KiB (458,752 B, 0.438 MiB) +
l2$ description	16-way set associative +
l2$ size	14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) +
l3$ description	11-way set associative +
l3$ size	19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	354.15 K (81 °C, 177.8 °F, 637.47 °R) +
max cpu count	4 +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	5117 +
name	Xeon Gold 5117 +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
s-spec	SR37S +
s-spec (qs)	QM8S +
series	5100 +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2400 +
tdp	105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technology	CMOS +
thread count	28 +
turbo frequency (1 core)	2,800 MHz (2.8 GHz, 2,800,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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Revision as of 13:23, 11 July 2017

Cache

Memory controller

Features