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Difference between revisions of "intel/xeon gold/6142m"
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|series=6100 | |series=6100 | ||
|locked=Yes | |locked=Yes | ||
− | |frequency=2 | + | |frequency=2,600 MHz |
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|clock multiplier=26 | |clock multiplier=26 | ||
|isa=x86-64 | |isa=x86-64 | ||
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|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
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|word size=64 bit | |word size=64 bit | ||
− | | | + | |core count=16 |
− | + | |thread count=32 | |
− | + | |tdp=150 W | |
− | | | + | |turbo frequency=Yes |
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|package module 1={{packages/intel/fclga-3647}} | |package module 1={{packages/intel/fclga-3647}} | ||
}} | }} | ||
− | '''Xeon Gold 6142M''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The | + | '''Xeon Gold 6142M''' is a {{arch|64}} [[x86]] high-performance server [[hexadeca-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6142 operates at 2.6 GHz with a TDP of 150 W and a {{intel|Turbo Boost|turbo frequency}} of 3.7 GHz. |
{{unknown features}} | {{unknown features}} | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1 MiB | ||
+ | |l1i cache=512 KiB | ||
+ | |l1i break=16x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=512 KiB | ||
+ | |l1d break=16x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=16 MiB | ||
+ | |l2 break=16x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=22 MiB | ||
+ | |l3 break=16x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem= | ||
+ | |controllers=1 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.89 GiB/s | ||
+ | |bandwidth dchan=39.72 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} | ||
== Features == | == Features == |
Revision as of 21:31, 8 July 2017
Template:mpu Xeon Gold 6142M is a 64-bit x86 high-performance server hexadeca-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6142 operates at 2.6 GHz with a TDP of 150 W and a turbo frequency of 3.7 GHz.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Gold 6142M - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6142M - Intel#io + |
base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 26 + |
core count | 16 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | H0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 25, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon gold/6142m + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Turbo Boost Technology 2.0 +, Speed Shift Technology +, Trusted Execution Technology +, Extended Page Tables + and Advanced Vector Extensions 512 + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max cpu count | 4 + |
max dts temperature | 99 °C + |
max memory | 1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 6142M + |
name | Xeon Gold 6142M + |
package | FCLGA-3647 + |
part number | CD8067303405700 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 5,949.00 (€ 5,354.10, £ 4,818.69, ¥ 614,710.17) + |
s-spec | SR3B1 + |
s-spec (qs) | QMRW + |
series | 6100 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 150 W (150,000 mW, 0.201 hp, 0.15 kW) + |
technology | CMOS + |
thread count | 32 + |
turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |