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Difference between revisions of "intel/xeon bronze/3106"
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(Created page with "{{intel title|Xeon Bronze 3106}} {{mpu |future=Yes |name=Xeon Bronze 3106 |no image=Yes |designer=Intel |manufacturer=Intel |model number=3106 |part number=CD8067303561900 |ma...")
 
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|technology=CMOS
 
|technology=CMOS
 
|word size=64 bit
 
|word size=64 bit
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|core count=6
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|core count=8
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|thread count=12
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|thread count=16
 
|package module 1={{packages/intel/fclga-3647}}
 
|package module 1={{packages/intel/fclga-3647}}
 
}}
 
}}
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'''Xeon Bronze 3104''' is a {{arch|64}} [[hexa-core]] [[x86]] server microprocessor set to be introduced by [[Intel]] in July 2017. This processor operates at 1.7 GHz
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'''Xeon Bronze 3104''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor set to be introduced by [[Intel]] in July 2017. This processor operates at 1.7 GHz
 
{{unknown features}}
 
{{unknown features}}
  
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{cache size
 
{{cache size
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|l1 cache=384 KiB
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|l1 cache=512 KiB
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|l1i cache=192 KiB
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|l1i cache=256 KiB
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|l1i break=6x32 KiB
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|l1i break=8x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
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|l1d cache=192 KiB
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|l1d cache=256 KiB
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|l1d break=6x32 KiB
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|l1d break=8x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d policy=write-back
 
|l1d policy=write-back
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|l2 cache=6 MiB
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|l2 cache=8 MiB
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|l2 break=6x1 MiB
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|l2 break=8x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back
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|l3 cache=8.25 MiB
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|l3 cache=11 MiB
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|l3 break=6x1.375 MiB
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|l3 break=8x1.375 MiB
 
|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
 
}}
 
}}

Revision as of 20:08, 8 July 2017

Template:mpu Xeon Bronze 3104 is a 64-bit octa-core x86 server microprocessor set to be introduced by Intel in July 2017. This processor operates at 1.7 GHz

DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
  8x1.375 MiB11-way set associativewrite-back
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Facts about "Xeon Bronze 3106 - Intel"
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l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +