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Difference between revisions of "intel/xeon gold/5120"
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Revision as of 20:04, 8 July 2017
Template:mpu Xeon Gold 5120 is a 64-bit 14-core x86 server microprocessor set to be introduced by Intel in July 2017. This processor operates at 2.2 GHz.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon Gold 5120 - Intel"
l1$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) + |