From WikiChip
Difference between revisions of "intel/core i7/i7-6820hq"
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|turbo frequency3=3,200 MHz | |turbo frequency3=3,200 MHz | ||
|turbo frequency4=3,200 MHz | |turbo frequency4=3,200 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=27 | ||
|isa=x86-64 | |isa=x86-64 | ||
+ | |isa family=x86 | ||
|microarch=Skylake | |microarch=Skylake | ||
|core name=Skylake H | |core name=Skylake H | ||
Line 28: | Line 33: | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
+ | |die area=122 mm² | ||
|word size=64 bit | |word size=64 bit | ||
|core count=4 | |core count=4 |
Revision as of 23:41, 7 July 2017
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i7-6820HQ - Intel"
has ecc memory support | false + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |