Difference between revisions of "intel/core i5/i5-6442eq"

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Revision as of 02:08, 7 July 2017

Template:mpu Core i5-6442EQ is a 64-bit quad-core mid-range performance x86 mobile microprocessor introduced by Intel in late 2015. This processor, which is based on the Skylake microarchitecture, is manufactured on Intel's improved 14 nm process. The i5-6442EQ operates at 1.9 GHz with a TDP of 25 W and with a Turbo Boost frequency of 2.7 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's HD Graphics 530 IGP operating at 350 MHz with a burst frequency of 1 GHz.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		4x256 KiB	4-way set associative	write-back

L3$

6 MiB

6,144 KiB
6,291,456 B
0.00586 GiB

		4x1.5 MiB		write-back

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Facts about "Core i5-6442EQ - Intel"

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Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core i5-6442EQ - Intel#package + and Core i5-6442EQ - Intel#io +
base frequency	1,900 MHz (1.9 GHz, 1,900,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
clock multiplier	19 +
core count	4 +
core family	6 +
core model	94 +
core name	Skylake H +
core stepping	R0 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.55 V (5.5 dV, 55 cV, 550 mV) +
designer	Intel +
device id	0x191B +
die area	122 mm² (0.189 in², 1.22 cm², 122,000,000 µm²) +
family	Core i5 +
first announced	October 12, 2015 +
first launched	October 12, 2015 +
full page name	intel/core i5/i5-6442eq +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	false +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, OS Guard +, Turbo Boost Technology 2.0 +, Trusted Execution Technology +, Intel vPro Technology +, Transactional Synchronization Extensions +, Secure Key Technology +, Identity Protection Technology +, Extended Page Tables +, Software Guard Extensions + and Memory Protection Extensions +
has intel enhanced speedstep technology	true +
has intel identity protection technology support	true +
has intel secure key technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics 530 +
integrated gpu base frequency	350 MHz (0.35 GHz, 350,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	24 +
integrated gpu max frequency	1,000 MHz (1 GHz, 1,000,000 KHz) +
integrated gpu max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	4-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size	6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
ldate	October 12, 2015 +
main image	+
manufacturer	Intel +
market segment	Embedded +
max cpu count	1 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	2 +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Skylake +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	i5-6442EQ +
name	Core i5-6442EQ +
package	FCBGA-1440 +
part number	CL8066202400005 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 250.00 (€ 225.00, £ 202.50, ¥ 25,832.50) +
s-spec	SR2DY +
series	i5-6000 +
smp max ways	1 +
supported memory type	LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 +
tdp	25 W (25,000 mW, 0.0335 hp, 0.025 kW) +
technology	CMOS +
thread count	4 +
turbo frequency (1 core)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (2 cores)	2,600 MHz (2.6 GHz, 2,600,000 kHz) +
turbo frequency (3 cores)	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
turbo frequency (4 cores)	2,400 MHz (2.4 GHz, 2,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

@@ Line 43: / Line 43: @@
 }}
 '''Core i5-6442EQ''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. This processor, which is based on the {{intel|Skylake|l=arch}} microarchitecture, is manufactured on Intel's improved [[14 nm process]]. The i5-6442EQ operates at 1.9 GHz with a TDP of 25 W and with a {{intel|Turbo Boost}} frequency of 2.7 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's {{intel|HD Graphics 530}} [[IGP]] operating at 350 MHz with a burst frequency of 1 GHz.
+== Cache ==
+{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
+{{cache size
+|l1 cache=256 KiB
+|l1i cache=128 KiB
+|l1i break=4x32 KiB
+|l1i desc=8-way set associative
+|l1d cache=128 KiB
+|l1d break=4x32 KiB
+|l1d desc=8-way set associative
+|l1d policy=write-back
+|l2 cache=1 MiB
+|l2 break=4x256 KiB
+|l2 desc=4-way set associative
+|l2 policy=write-back
+|l3 cache=6 MiB
+|l3 break=4x1.5 MiB
+|l3 policy=write-back
+}}

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Revision as of 02:08, 7 July 2017

Cache