From WikiChip
					
    Difference between revisions of "intel/core i7/i7-6560u"    
                	
														| Line 9: | Line 9: | ||
|s-spec=SR2JB  | |s-spec=SR2JB  | ||
|market=Mobile  | |market=Mobile  | ||
| + | |first announced=September 1, 2015  | ||
| + | |first launched=September 27, 2015  | ||
|family=Core i7  | |family=Core i7  | ||
|series=i7-6000  | |series=i7-6000  | ||
| Line 14: | Line 16: | ||
|frequency=2,200 MHz  | |frequency=2,200 MHz  | ||
|turbo frequency1=3,200 MHz  | |turbo frequency1=3,200 MHz  | ||
| + | |turbo frequency2=3,100 MHz  | ||
|bus type=OPI  | |bus type=OPI  | ||
|bus rate=4 GT/s  | |bus rate=4 GT/s  | ||
Revision as of 13:19, 6 July 2017
Template:mpu Core i7-6560U is a 64-bit dual-core high-end performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.2 GHz with a turbo boost of up to 3.2 GHz. The i7-6560U has a TDP of 15 W with a configurable-down TDP of 9.5 W. This chip incorporates the Iris Graphics 540 GPU operating at 300 MHz with a burst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory. The 6560U comes with an additional 64 MiB of embedded DRAM side cache.
Cache
- Main article: Skylake § Cache
 
| 
 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
|||||||||||||||||||||||||||||||||||||||||||||||||
  | 
|||||||||||||||||||||||||||||||||||||||||||||||||
Memory controller
| 
 Integrated Memory Controller 
 | 
||||||||||||||
  | 
||||||||||||||
Expansions
| 
 Expansion Options 
 | 
||||||||
  | 
||||||||
Graphics
The Iris Plus Graphics 540 includes 64 MiB of side eDRAM cache in addition to everything else.
| 
 Integrated Graphics Information 
 | 
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
  | 
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| [Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
|---|---|---|---|---|---|---|---|
| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
| MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
| JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
| HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
| VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
| VP9 | ✘ | 0 | Unified | 2160p (4K) | |||
Features
[Edit/Modify Supported Features]
Facts about "Core i7-6560U  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | Core i7-6560U - Intel#io + | 
| device id | 0x1926 + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has ecc memory support | false + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology + and Identity Protection Technology + | 
| has intel enhanced speedstep technology | true + | 
| has intel flex memory access support | true + | 
| has intel identity protection technology support | true + | 
| has intel my wifi technology support | true + | 
| has intel secure key technology | true + | 
| has intel smart response technology support | true + | 
| has intel supervisor mode execution protection | true + | 
| has intel turbo boost technology 2 0 | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| integrated gpu | Iris Plus Graphics 540 + | 
| integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + | 
| integrated gpu designer | Intel + | 
| integrated gpu execution units | 48 + | 
| integrated gpu max frequency | 1,050 MHz (1.05 GHz, 1,050,000 KHz) + | 
| integrated gpu max memory | 32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB) + | 
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + | 
| l2$ description | 4-way set associative + | 
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + | 
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + | 
| l4$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + | 
| max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + | 
| max memory channels | 2 + | 
| max pcie lanes | 12 + | 
| supported memory type | DDR4-2133 +, LPDDR3-1866 + and DDR3L-1600 + | 
| x86/has memory protection extensions | true + | 
| x86/has software guard extensions | true + |