Revision as of 19:16, 3 July 2017

Template:mpu Core i7-6650U is a 64-bit dual-core high-end performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.2 GHz with a turbo boost of up to 3.4 GHz. The i7-6650U has a TDP of 15 W with a configurable-down TDP of 9.5 W. This chip incorporates the Iris Graphics 540 GPU operating at 300 MHz with a burst frequency of 1.05 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative write-back L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 4-way set associative write-back L3$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     2x2 MiB   write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2133, LPDDR3-1866, DDR3L-1600 Supports ECC No Max Mem 32 GiB Controllers 1 Channels 2 Max Bandwidth 31.79 GiB/s 32,552.96 MiB/s 34.134 GB/s 34,134.253 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Single 15.89 GiB/s Double 31.79 GiB/s

Expansions

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	Expansion Options
	PCIe Revision 3.0 Max Lanes 12 Configs 1x4, 2x2, 1x2+2x1, 4x1

Graphics

Features

Template:mpu features