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Difference between revisions of "intel/core i5/i5-6200u"
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'''Core i5-6200U''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.30 GHz with a {{intel|turbo boost}} of up to 2.80 GHz. The i5-6200U has a TDP of 15 W with a configurable-down TDP of 7.5 W (800 MHz) and a configurable-up TDP of 25 (2.4 GHz). This chip incorporates the {{intel|HD Graphics 520}} GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
 
'''Core i5-6200U''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in late [[2015]]. Fabricated on a [[14 nm process]] based on the {{intel|Skylake}} microarchitecture, this processor operates at 2.30 GHz with a {{intel|turbo boost}} of up to 2.80 GHz. The i5-6200U has a TDP of 15 W with a configurable-down TDP of 7.5 W (800 MHz) and a configurable-up TDP of 25 (2.4 GHz). This chip incorporates the {{intel|HD Graphics 520}} GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.
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== Cache ==
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
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{{cache size
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|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=2x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=64 KiB
 +
|l1d break=2x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
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|l2 cache=512 KiB
 +
|l2 break=2x256 KiB
 +
|l2 desc=4-way set associative
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|l2 policy=write-back
 +
|l3 cache=3 MiB
 +
|l3 break=2x1.5 MiB
 +
|l3 policy=write-back
 +
}}

Revision as of 18:44, 3 July 2017

Template:mpu Core i5-6200U is a 64-bit dual-core mid-range performance x86 mobile microprocessor introduced by Intel in late 2015. Fabricated on a 14 nm process based on the Skylake microarchitecture, this processor operates at 2.30 GHz with a turbo boost of up to 2.80 GHz. The i5-6200U has a TDP of 15 W with a configurable-down TDP of 7.5 W (800 MHz) and a configurable-up TDP of 25 (2.4 GHz). This chip incorporates the HD Graphics 520 GPU operating at 300 MHz with a burst frequency of 1 GHz. This processor supports up to 32 GiB of non-ECC dual-channel DDR4-2133 memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB write-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i5/i5-6200u&oldid=50181"
Facts about "Core i5-6200U - Intel"
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l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +