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Difference between revisions of "intrinsity/fastmath/fastmath-lp"
< intrinsity‎ | fastmath

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| model number        = FastMATH-LP
 
| model number        = FastMATH-LP
 
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| part number        =  
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| part number 1       =  
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| part number 2       =  
 
| market              = Embedded
 
| market              = Embedded
 
| first announced    = 2002
 
| first announced    = 2002

Revision as of 17:52, 30 June 2017

Template:mpu The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.

Cache

Main article: FastMATH § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block
L1D$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block write-through or write-back mode
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR-400
Controllers 1
Channels 2
Max memory 1 GB

Matrix and Vector Unit

  • SIMD architecture
  • Operates on 4x4 array of 32-bit elements
  • Fixed-point matrix, vector, and scalar data types

Features

  • JTAG interface
  • 8-bit or 32-bit wide bus operates up to 66 MHz

Documents

Manuals


Retrieved from "https://en.wikichip.org/w/index.php?title=intrinsity/fastmath/fastmath-lp&oldid=49701"
Facts about "FastMATH-LP - Intrinsity"
RDF feed
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus speed500 MHz (0.5 GHz, 500,000 kHz) +
bus typeRapidIO +
core count1 +
core voltage0.85 V (8.5 dV, 85 cV, 850 mV) +
designerIntrinsity +
familyFastMATH +
first announced2002 +
first launched2003 +
full page nameintrinsity/fastmath/fastmath-lp +
has featureJTAG +
instance ofmicroprocessor +
l1d$ description256 blocks × 16 words/block +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description256 blocks × 16 words/block +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate2003 +
main imageFile:fastmath-lp chip.gif +
manufacturerTSMC +
market segmentEmbedded +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
microarchitectureFashMATH +
model numberFastMATH-LP +
nameFastMATH-LP +
power dissipation6 W (6,000 mW, 0.00805 hp, 0.006 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyDynamic CMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +