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Difference between revisions of "cavium/octeon plus/cn5860-1000bg1521-scp"
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| model number = CN5860-1000 SCP | | model number = CN5860-1000 SCP | ||
| part number = CN5860-1000BG1521-SCP | | part number = CN5860-1000BG1521-SCP | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Network | | market = Network | ||
| first announced = October 9, 2006 | | first announced = October 9, 2006 | ||
Revision as of 18:15, 30 June 2017
Template:mpu CN5860-1000 SCP is a 64-bit hexadeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
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Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN5860-1000 SCP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5860-1000 SCP - Cavium#package + |
| base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + |
| core count | 16 + |
| designer | Cavium + |
| family | OCTEON Plus + |
| first announced | October 9, 2006 + |
| first launched | February 2007 + |
| full page name | cavium/octeon plus/cn5860-1000bg1521-scp + |
| has ecc memory support | true + |
| has hardware accelerators for cryptography | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| instance of | microprocessor + |
| isa | MIPS64 + |
| isa family | MIPS + |
| l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 64-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| ldate | February 2007 + |
| main image | |
| manufacturer | TSMC + |
| market segment | Network + |
| max cpu count | 1 + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| microarchitecture | cnMIPS + |
| model number | CN5860-1000 SCP + |
| name | Cavium CN5860-1000 SCP + |
| package | FCBGA-1521 + |
| part number | CN5860-1000BG1521-SCP + |
| power dissipation | 40 W (40,000 mW, 0.0536 hp, 0.04 kW) + |
| process | 90 nm (0.09 μm, 9.0e-5 mm) + |
| release price | $ 987.00 (€ 888.30, £ 799.47, ¥ 101,986.71) + |
| series | CN58xx + |
| smp max ways | 1 + |
| supported memory type | DDR2-800 + |
| technology | CMOS + |
| thread count | 16 + |
| word size | 64 bit (8 octets, 16 nibbles) + |