From WikiChip
Difference between revisions of "intel/core i5/i5-8250u"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
|||
Line 1: | Line 1: | ||
{{intel title|Core i5-8250U}} | {{intel title|Core i5-8250U}} | ||
{{mpu | {{mpu | ||
− | | future | + | |future=Yes |
− | | name | + | |name=Core i5-8250U |
− | | no image | + | |no image=Yes |
− | + | |designer=Intel | |
− | + | |manufacturer=Intel | |
− | + | |model number=i5-8250U | |
− | | designer | + | |market=Mobile |
− | | manufacturer | + | |first announced=June, 2017 |
− | | model number | + | |family=Core i5 |
− | + | |series=i5-8200 | |
− | + | |locked=Yes | |
− | + | |frequency=1,800 MHz | |
− | + | |bus type=OPI | |
− | + | |bus rate=4 GT/s | |
− | | market | + | |clock multiplier=18 |
− | | first announced | + | |isa=x86-64 |
− | + | |isa family=x86 | |
− | + | |microarch=Coffee Lake | |
− | + | |platform=Coffee Lake | |
− | + | |core name=Coffee Lake U | |
− | + | |core family=6 | |
− | | family | + | |core model=142 |
− | | series | + | |process=14 nm |
− | | locked | + | |technology=CMOS |
− | | frequency | + | |word size=64 bit |
− | + | |core count=4 | |
− | + | |thread count=4 | |
− | + | |max cpus=1 | |
− | + | |max memory=32 GiB | |
− | + | |v core min=0.55 V | |
− | | bus type | + | |v core max=1.52 V |
− | + | |tdp=15 W | |
− | | bus rate | + | |tjunc min=0 °C |
− | + | |tjunc max=100 °C | |
− | | clock multiplier | + | |tstorage min=-25 °C |
− | + | |tstorage max=125 °C | |
− | + | |turbo frequency=Yes | |
− | | isa | ||
− | | isa | ||
− | | microarch | ||
− | | platform | ||
− | |||
− | | core name | ||
− | | core family | ||
− | | core model | ||
− | |||
− | |||
− | | process | ||
− | |||
− | | technology | ||
− | |||
− | |||
− | |||
− | | word size | ||
− | | core count | ||
− | | thread count | ||
− | | max cpus | ||
− | | max memory | ||
− | |||
− | |||
− | | v core min | ||
− | | v core max | ||
− | |||
− | | tdp | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | | tjunc min | ||
− | | tjunc max | ||
− | |||
− | |||
− | | tstorage min | ||
− | | tstorage max | ||
− | | | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
}} | }} | ||
'''Core i5-8250U''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile microprocessor set to be introduced by [[Intel]] in mid-[[2017]]. This chip, which is based on the {{intel|Coffee Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm++ process]]. The i5-8250U operates at 1.8 GHz with a TDP of 15 W supporting a {{intel|Turbo Boost}} frequency of ? GHz. The processor supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory. | '''Core i5-8250U''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile microprocessor set to be introduced by [[Intel]] in mid-[[2017]]. This chip, which is based on the {{intel|Coffee Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm++ process]]. The i5-8250U operates at 1.8 GHz with a TDP of 15 W supporting a {{intel|Turbo Boost}} frequency of ? GHz. The processor supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory. |
Revision as of 02:55, 29 June 2017
Template:mpu Core i5-8250U is a 64-bit quad-core mid-range performance x86 mobile microprocessor set to be introduced by Intel in mid-2017. This chip, which is based on the Coffee Lake microarchitecture, is fabricated on Intel's 14nm++ process. The i5-8250U operates at 1.8 GHz with a TDP of 15 W supporting a Turbo Boost frequency of ? GHz. The processor supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory.
Cache
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options
|
||||||||
|
Graphics
This section is empty; you can help add the missing info by editing this page. |
Features
[Edit/Modify Supported Features]
Facts about "Core i5-8250U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-8250U - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel my wifi technology support | true + |
has intel secure key technology | true + |
has intel smart response technology support | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 12 + |
supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |