From WikiChip
Difference between revisions of "intel/xeon e3/e3-1275 v6"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
|||
Line 1: | Line 1: | ||
{{intel title|Xeon E3-1275 v6}} | {{intel title|Xeon E3-1275 v6}} | ||
{{mpu | {{mpu | ||
− | | name | + | |name=Xeon E3-1275 v6 |
− | | no image | + | |no image=Yes |
− | + | |designer=Intel | |
− | + | |manufacturer=Intel | |
− | + | |model number=E3-1275 v6 | |
− | | designer | + | |part number=CM8067702870931 |
− | | manufacturer | + | |part number 2=BX80677E31275V6 |
− | | model number | + | |s-spec=SR32A |
− | | part number | + | |market=Workstation |
− | | part number 2 | + | |market 2=Server |
− | | s-spec | + | |first announced=March 28, 2017 |
− | | market | + | |first launched=March 28, 2017 |
− | | market 2 | + | |release price=$339 |
− | | first announced | + | |family=Xeon E3 |
− | | first launched | + | |series=E3-1200 v6 |
− | + | |locked=Yes | |
− | + | |frequency=3,800 MHz | |
− | | release price | + | |turbo frequency1=4,200 MHz |
− | + | |bus type=DMI 3.0 | |
− | | family | + | |bus rate=8 GT/s |
− | | series | + | |clock multiplier=38 |
− | | locked | + | |isa=x86-64 |
− | | frequency | + | |isa family=x86 |
− | + | |microarch=Kaby Lake | |
− | | turbo frequency1 | + | |platform=Greenlow |
− | + | |chipset=Sunrise Point | |
− | + | |chipset 2=Union Point | |
− | + | |core name=Kaby Lake DT | |
− | | bus type | + | |core family=6 |
− | + | |core stepping=B0 | |
− | | bus rate | + | |process=14 nm |
− | + | |technology=CMOS | |
− | | clock multiplier | + | |word size=64 bit |
− | + | |core count=4 | |
− | + | |thread count=8 | |
− | | isa | + | |max cpus=1 |
− | | isa | + | |max memory=64 GiB |
− | | microarch | + | |v core min=0.55 V |
− | | platform | + | |v core max=1.52 V |
− | | chipset | + | |tdp=73 W |
− | | chipset 2 | + | |tstorage min=-25 °C |
− | | core name | + | |tstorage max=125 °C |
− | | core family | + | |package module 1={{packages/intel/lga-1151}} |
− | + | |turbo frequency=Yes | |
− | | core stepping | ||
− | |||
− | | process | ||
− | |||
− | | technology | ||
− | |||
− | |||
− | |||
− | | word size | ||
− | | core count | ||
− | | thread count | ||
− | | max cpus | ||
− | | max memory | ||
− | |||
− | |||
− | | v core min | ||
− | | v core max | ||
− | |||
− | | tdp | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | | tstorage min | ||
− | | tstorage max | ||
− | |||
− | |||
− | |||
− | | package module 1 | ||
}} | }} | ||
'''Xeon E3-1275 v6''' is a {{arch|64}} [[quad-core]] [[x86]] workstation/entry server microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The E3-1275 v6 operates at 3.8 GHz with a TDP of 73 W supporting a {{intel|Turbo Boost}} frequency of 4.2 GHz. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory and incorporates Intel's {{intel|HD Graphics P630}} [[IGP]] operating at 350 MHz with a burst frequency of 1.15 GHz. | '''Xeon E3-1275 v6''' is a {{arch|64}} [[quad-core]] [[x86]] workstation/entry server microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The E3-1275 v6 operates at 3.8 GHz with a TDP of 73 W supporting a {{intel|Turbo Boost}} frequency of 4.2 GHz. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory and incorporates Intel's {{intel|HD Graphics P630}} [[IGP]] operating at 350 MHz with a burst frequency of 1.15 GHz. |
Revision as of 03:30, 27 June 2017
Template:mpu Xeon E3-1275 v6 is a 64-bit quad-core x86 workstation/entry server microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The E3-1275 v6 operates at 3.8 GHz with a TDP of 73 W supporting a Turbo Boost frequency of 4.2 GHz. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory and incorporates Intel's HD Graphics P630 IGP operating at 350 MHz with a burst frequency of 1.15 GHz.
Cache
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options
|
||||||||
|
Graphics
Integrated Graphics Information
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
[Edit] Kaby Lake (Gen9.5) Hardware Accelerated Video Capabilities | |||||||
---|---|---|---|---|---|---|---|
Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, MVC, Stereo | 5.1 | 2160p (4K) | |
JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
HEVC (H.265) | Main, Main 10 | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | 3840x3840 | |||
VP8 | Unified | Unified | N/A | 0 | Unified | 1080p | |
VP9 | 0 | 2160p (4K) | 0, 2 | Unified | 2160p (4K) |
Features
[Edit/Modify Supported Features]
Facts about "Xeon E3-1275 v6 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1275 v6 - Intel#package + and Xeon E3-1275 v6 - Intel#io + |
base frequency | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Sunrise Point + and Union Point + |
clock multiplier | 38 + |
core count | 4 + |
core family | 6 + |
core model | 158 + |
core name | Kaby Lake DT + |
core stepping | B0 + |
core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + |
core voltage (min) | 0.55 V (5.5 dV, 55 cV, 550 mV) + |
designer | Intel + |
device id | 0x591D + |
family | Xeon E3 + |
first announced | March 28, 2017 + |
first launched | March 28, 2017 + |
full page name | intel/xeon e3/e3-1275 v6 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Secure Key Technology +, Enhanced SpeedStep Technology +, OS Guard +, Extended Page Tables +, Memory Protection Extensions + and Software Guard Extensions + |
has intel enhanced speedstep technology | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics P630 + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 1,150 MHz (1.15 GHz, 1,150,000 KHz) + |
integrated gpu max memory | 1,740.8 MiB (1,782,579.2 KiB, 1,825,361,100.8 B, 1.7 GiB) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
ldate | March 28, 2017 + |
manufacturer | Intel + |
market segment | Workstation + and Server + |
max cpu count | 1 + |
max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Kaby Lake + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | E3-1275 v6 + |
name | Xeon E3-1275 v6 + |
package | FCLGA-1151 + |
part number | CM8067702870931 + and BX80677E31275V6 + |
platform | Greenlow + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 339.00 (€ 305.10, £ 274.59, ¥ 35,028.87) + |
s-spec | SR32A + |
series | E3-1200 v6 + |
smp max ways | 1 + |
socket | LGA-1151 + |
supported memory type | DDR4-2400 + and DDR3L-1866 + |
tdp | 73 W (73,000 mW, 0.0979 hp, 0.073 kW) + |
technology | CMOS + |
thread count | 8 + |
turbo frequency (1 core) | 4,200 MHz (4.2 GHz, 4,200,000 kHz) + |
turbo frequency (2 cores) | 4,100 MHz (4.1 GHz, 4,100,000 kHz) + |
turbo frequency (3 cores) | 4,100 MHz (4.1 GHz, 4,100,000 kHz) + |
turbo frequency (4 cores) | 4,000 MHz (4 GHz, 4,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |