Difference between revisions of "amd/k5/amd-k5-pr75abr"

From WikiChip

< amd‎ | k5

Revision as of 20:52, 23 June 2017

Template:mpu AMD-K5-PR75ABR was a 32-bit x86 microprocessor developed by AMD and released in 1996. This chip was sold as Pentium 75 MHz equivalent. The processor used AMD's 2nd revision of their K5 microarchitecture, operating at 75 MHz with a TDP of 11.8 W.

1 Cache
2 Die Shot
3 Graphics
4 Features
5 See also

Cache

Main article: K5 § Cache

Cache Info [Edit Values]
L1I$	16 KiB 16,384 B 0.0156 MiB	1x16 KiB 4-way set associative
L1D$	8 KiB 8,192 B 0.00781 MiB	1x8 KiB 4-way set associative

Die Shot

Graphics

This SoC has no integrated graphics processing unit.

Features

P75 P-Rating
Auto-power down state
Stop clock state

base frequency	75 MHz (0.075 GHz, 75,000 kHz) +
bus rate	50 MT/s (0.05 GT/s, 50,000 kT/s) +
bus speed	50 MHz (0.05 GHz, 50,000 kHz) +
bus type	FSB +
clock multiplier	1.5 +
core count	1 +
core family	5 +
core model	0 +
core name	SSA/5 +
core stepping	1 +
core voltage	3.525 V (35.25 dV, 352.5 cV, 3,525 mV) +
core voltage tolerance	2% +
cpuid	501 +
designer	AMD +
die area	161 mm² (0.25 in², 1.61 cm², 161,000,000 µm²) +
family	K5 +
first announced	1996 +
first launched	October 7, 1996 +
full page name	amd/k5/amd-k5-pr75abr +
instance of	microprocessor +
l1d$ description	4-way set associative +
l1d$ size	8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description	4-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
ldate	October 7, 1996 +
manufacturer	AMD +
market segment	Desktop +
max case temperature	343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count	1 +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory address	0xFFFFFFFF +
max storage temperature	423.15 K (150 °C, 302 °F, 761.67 °R) +
microarchitecture	K5 +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	208.15 K (-65 °C, -85 °F, 374.67 °R) +
model number	AMD-K5-PR75ABR +
name	AMD-K5-PR75ABR +
part number	AMD-K5-PR75ABR +
power dissipation	11.8 W (11,800 mW, 0.0158 hp, 0.0118 kW) +
process	350 nm (0.35 μm, 3.5e-4 mm) +
processor p-rating	P75 +
series	SSA/5 +
smp max ways	1 +
technology	CMOS +
thread count	1 +
transistor count	4,300,000 +
word size	32 bit (4 octets, 8 nibbles) +

@@ Line 45: / Line 45: @@
 | max memory addr     = 0xFFFFFFFF
-| electrical          = Yes
 | power               = 11.8 W
 | v core              = 3.525 V

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas