Semiconductor & Computer Engineering
(→Expansions) |
(→Memory controller) |
||
| Line 91: | Line 91: | ||
== Memory controller == | == Memory controller == | ||
| − | {{ | + | {{memory controller |
| − | | type | + | |type=DDR3-1333 |
| − | | controllers | + | |ecc=Yes |
| − | | channels | + | |controllers=4 |
| − | | | + | |channels=4 |
| − | | bandwidth | + | |width=64 bit |
| − | | bandwidth | + | |max bandwidth=39.74 GiB/s |
| − | | bandwidth | + | |bandwidth schan=9.93 GiB/s |
| − | | | + | |bandwidth dchan=19.86 GiB/s |
| + | |bandwidth qchan=39.74 GiB/ | ||
}} | }} | ||
Revision as of 06:36, 23 June 2017
Template:mpu PEZY-1 was a first generation many-core microprocessor developed by PEZY in 2012. PEZY-1 contains 2 ARM926 cores (ARMv5TEJ) along with 512 simpler RISC cores. Operating at 533 MHz, the processor is said to have peach performance of 533 GFLOPS (single-precision) and 266 GFLOPS (double-precision). PEZY-1 was designed using 220 million gates and manufactured on TSMC's 40 nm process.
The PEZY-1 is used for image processing devices and various medical instruments. In 2014 PEZY introduced their second generation many-core processor, the PEZY-SC, with twice as many cores.
Cache
PEZY-1's cache is separate from the ARM926's cache which has an L1$ of 16KB (2x) and no L2$.
| Cache Info [Edit Values] | ||
| L1$ | 128 KiB 131,072 B 0.125 MiB |
|
| L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
|
| L3$ | 0 KiB 0 MiB 0 B 0 GiB |
No L3$ |
Memory controller
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
Expansions
 |
Expansion Options
|
|||||||||||
|
||||||||||||
PEZY-1 Quad PCI Board
PEZY has developed a Quad-PEZY-1 PCI board for their microprocessors which has 4 PEZY-1 for a total of 2,048 PE cores (along with 8 ARM cores). The board is equipped with 64 GB of memory for a total bandwidth of 200 GB/s. PEZY reports the total computational power for the board to be at 2.56 TFLOPS with a power consumption of 180 Watts.
Documents
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-1 - PEZY#io + |
| has ecc memory support | true + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | No L3$ + |
| l3$ size | 0 MiB (0 KiB, 0 B, 0 GiB) + |
| max memory bandwidth | 39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) + |
| max memory channels | 4 + |
| max pcie lanes | 4 + |
| supported memory type | DDR3-1333 + |