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Difference between revisions of "compaq/microarchitectures/alpha 21364"
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| + | |||
| + | == Documents == | ||
| + | * [[:File:Alpha 21364 (EV7) (January 4, 2002).pdf|Alpha 21364 (EV7)]], January 4, 2002 | ||
| + | * [[:File:ev7SMP.ppt|Alpha 21364: A Scalable Single-chip SMP (PPT)]] ([[:File:ev7SMP.pdf|PDF Version]]), 1998 | ||
== References == | == References == | ||
* "Alpha 21364 (EV7)", Compaq presentation | * "Alpha 21364 (EV7)", Compaq presentation | ||
* Tsuk, M., et al. "Modeling and measurement of the Alpha 21364 package." Electrical Performance of Electronic Packaging, 2001. IEEE, 2001. | * Tsuk, M., et al. "Modeling and measurement of the Alpha 21364 package." Electrical Performance of Electronic Packaging, 2001. IEEE, 2001. | ||
Revision as of 01:48, 12 June 2017
| Edit Values | |
| Alpha 21364 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | DEC, Compaq |
| Manufacturer | IBM |
| Introduction | January 20, 2002 |
| Process | 0.18 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 6 |
| Decode | 4-way |
| Instructions | |
| ISA | Alpha |
| Cache | |
| L1I Cache | 64 KiB/core 2-way set associative |
| L1D Cache | 64 KiB/core 2-way set associative |
| L2 Cache | 1.75 MiB/core 7-way set associative |
| Succession | |
Alpha 21364 was an Alpha microarchitecture designed by Compaq after acquiring it from DEC and introduced in 2002 as a successor to the Alpha 21264 architecture.
History
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This section is empty; you can help add the missing info by editing this page. |
Process Technology
- See also: 0.18 µm process
| |
This section is empty; you can help add the missing info by editing this page. |
Architecture
| |
This section is empty; you can help add the missing info by editing this page. |
Die
- 1,250 MHz
- 135 Watts (155 W peak) @ 1.65 volts
- 0.18 µm process
- 7 metal layers (copper interconnect)
- 152,000,000 transistors
- 15,000,000 logic
- 137,000,000 cache
- 21.1 mm x 18.8 mm
- 396.68 mm² die size
- PGA-1443 package
- 946 signal pins
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Core
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Documents
- Alpha 21364 (EV7), January 4, 2002
- Alpha 21364: A Scalable Single-chip SMP (PPT) (PDF Version), 1998
References
- "Alpha 21364 (EV7)", Compaq presentation
- Tsuk, M., et al. "Modeling and measurement of the Alpha 21364 package." Electrical Performance of Electronic Packaging, 2001. IEEE, 2001.
Facts about "Alpha 21364 - Microarchitectures - Compaq"
| codename | Alpha 21364 + |
| core count | 1 + |
| designer | DEC + and Compaq + |
| first launched | January 20, 2002 + |
| full page name | compaq/microarchitectures/alpha 21364 + |
| instance of | microarchitecture + |
| instruction set architecture | Alpha + |
| manufacturer | IBM + |
| microarchitecture type | CPU + |
| name | Alpha 21364 + |
| pipeline stages | 6 + |
| process | 180 nm (0.18 μm, 1.8e-4 mm) + |