Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon e3/e3-1270 v5"
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== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| − | | | + | |real=Yes |
| − | | nx | + | |protected=Yes |
| − | | | + | |smm=Yes |
| − | | | + | |fpu=Yes |
| − | | | + | |x8616=Yes |
| − | | | + | |x8632=Yes |
| − | | | + | |x8664=Yes |
| − | | | + | |nx=Yes |
| − | | | + | |mmx=Yes |
| − | | | + | |emmx=Yes |
| − | | | + | |sse=Yes |
| − | | | + | |sse2=Yes |
| − | | | + | |sse3=Yes |
| − | | | + | |ssse3=Yes |
| − | | | + | |sse41=Yes |
| − | | | + | |sse42=Yes |
| − | | | + | |sse4a=No |
| − | | | + | |avx=Yes |
| − | | | + | |avx2=Yes |
| − | | | + | |avx512=No |
| − | | | + | |abm=Yes |
| − | | | + | |tbm=No |
| − | | | + | |bmi1=Yes |
| − | | | + | |bmi2=Yes |
| − | | | + | |fma3=Yes |
| − | | | + | |fma4=No |
| − | | | + | |aes=Yes |
| − | | | + | |rdrand=Yes |
| − | | | + | |sha=No |
| − | | mpx | + | |xop=No |
| − | | sgx | + | |adx=Yes |
| − | | | + | |clmul=Yes |
| − | | | + | |f16c=Yes |
| − | | | + | |tbt1=No |
| + | |tbt2=No | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=Yes | ||
| + | |sst=Yes | ||
| + | |flex=No | ||
| + | |fastmem=No | ||
| + | |isrt=No | ||
| + | |sba=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=Yes | ||
| + | |txt=Yes | ||
| + | |ht=Yes | ||
| + | |vpro=Yes | ||
| + | |vtx=Yes | ||
| + | |vtd=Yes | ||
| + | |ept=Yes | ||
| + | |mpx=Yes | ||
| + | |sgx=Yes | ||
| + | |securekey=Yes | ||
| + | |osguard=Yes | ||
| + | |3dnow=No | ||
| + | |e3dnow=No | ||
| + | |smartmp=No | ||
| + | |powernow=No | ||
| + | |amdvi=No | ||
| + | |amdv=No | ||
| + | |rvi=No | ||
| + | |smt=No | ||
| + | |sensemi=No | ||
| + | |xfr=No | ||
}} | }} | ||
Revision as of 10:20, 3 June 2017
Template:mpu Xeon E3-1270 V5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.6 GHz with turbo boost of 4 GHz. The E3-1270 V5 has a TDP of 80 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has no integrated graphics processor.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
This chip has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
Facts about "Xeon E3-1270 v5 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1270 v5 - Intel#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology + and OS Guard + |
| has intel enhanced speedstep technology | true + |
| has intel secure key technology | true + |
| has intel speed shift technology | true + |
| has intel supervisor mode execution protection | true + |
| has intel trusted execution technology | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3L-1600 + and DDR4-2133 + |
| x86/has memory protection extensions | true + |
| x86/has software guard extensions | true + |