From WikiChip
Difference between revisions of "intel/xeon e3/e3-1260l v5"
< intel

Line 97: Line 97:
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3L-1600
 +
|type 2=DDR4-2133
 +
|ecc=Yes
 +
|max mem=64 GiB
 +
|controllers=1
 +
|channels=2
 +
|max bandwidth=35.76 GiB/s
 +
|bandwidth schan=17.88 GiB/s
 +
|bandwidth dchan=35.76 GiB/s
 
}}
 
}}
  
 
== Graphics ==
 
== Graphics ==
 
This chip has no integrated graphics processing unit.
 
This chip has no integrated graphics processing unit.
−
 
−
== Memory controller ==
 
−
{{integrated memory controller
 
−
| type              = DDR3L-1333
 
−
| type 2            = DDR3L-1600
 
−
| type 3            = DDR3L-RS1333
 
−
| type 4            = DDR3L-RS1600
 
−
| type 5            = DDR4-1866
 
−
| type 6            = DDR4-2133
 
−
| type 7            = DDR4-RS1866
 
−
| type 8            = DDR4-RS2133
 
−
| controllers        = 1
 
−
| channels          = 2
 
−
| ecc support        = Yes
 
−
| max bandwidth      = 34.1 GB/s
 
−
| bandwidth schan    =
 
−
| bandwidth dchan    =
 
−
| max memory        = 64 GB
 
−
}}
 
  
 
== Expansions ==
 
== Expansions ==

Revision as of 09:27, 3 June 2017

Template:mpu Xeon E3-1260L V5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 2.9 GHz with turbo boost of 3.9 GHz. The E3-1260L V5 is a special low-power chip with a TDP of 45 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has no integrated graphics processor.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, DDR4-2133
Supports ECCYes
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth35.76 GiB/s
36,618.24 MiB/s
38.397 GB/s
38,397.008 MB/s
0.0349 TiB/s
0.0384 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s

Graphics

This chip has no integrated graphics processing unit.

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e3/e3-1260l_v5&oldid=43967"
Facts about "Xeon E3-1260L v5 - Intel"
RDF feed
has ecc memory supporttrue +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
max memory bandwidth35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
supported memory typeDDR3L-1600 + and DDR4-2133 +