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'''Cortex-A75''' is a low-power high-performance [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A73|l=arch}}. The Cortex-A75, which implemented the {{arm|ARMv8}} ISA, is typically is a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
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Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.

Revision as of 09:08, 29 May 2017

Edit Values
Cortex-A75 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionMay 29, 2017
Process16 nm, 14 nm, 10 nm, 7 nm
Core Configs1, 2
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages11-13
Decode3-way
Instructions
ISAARMv8
ExtensionsFPU, NEON
Cache
L1I Cache8-64 KiB/core
4-way set associative
L1D Cache8-64 KiB/core
4-way set associative
L2 Cache64-256-512 KiB/core
L3 Cache0-4 MiB/Cluster
Succession

Cortex-A75 is a low-power high-performance microarchitecture designed by ARM Holdings as a successor to the Cortex-A73. The Cortex-A75, which implemented the ARMv8 ISA, is typically is a performant core which is often combined with a number of lower power cores (e.g. Cortex-A55) in a DynamIQ big.LITTLE configuration to achieve better energy/performance.

Note that this microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

codenameCortex-A75 +
core count1 + and 2 +
designerARM Holdings +
first launchedMay 29, 2017 +
full page namearm holdings/microarchitectures/cortex-a75 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A75 +
pipeline stages (max)13 +
pipeline stages (min)11 +
process16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +