Difference between revisions of "WikiChip:sandbox"

Revision as of 02:51, 14 May 2017

Welcome to this sandbox page. Sandbox pages provide space to experiment with the process of editing.

ssssssssssss

DATA BUS I/O		D₀	01		16	CM-RAM₀		X

		D₁	02		15	CM-RAM₁	X

		D₂	03		14	CM-RAM₂	X

		D₃	04		13	CM-RAM₃	X

		V_ss	05		12	V_dd	X

CLOCK PHASE 1/2		Ø₁	06		11	CM-ROM	X

		Ø₂	07		10	TEST	X

		SYNC	08		09	RESET	X

1	2	3	4	5	6	7	8	9

Cache Info

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes.

[Edit Values]

L1$

128 KiB

L1I$	64 KiB	1x64 KiB	2-way set associative	write-back
L1D$	64 KiB	1x64 KiB	2-way set associative	write-back

L2$

128 KiB

L2I$	64 KiB	1x64 KiB	2-way set associative	write-back
L2D$	64 KiB	1x64 KiB	2-way set associative	write-back

L3$

128 KiB

L3I$	64 KiB	1x64 KiB	2-way set associative	write-back
L3D$	64 KiB	1x64 KiB	2-way set associative	write-back

L4$

128 KiB

L4I$	64 KiB	1x64 KiB	2-way set associative	write-back
L4D$	64 KiB	1x64 KiB	2-way set associative	write-back

Off-package cache support

Mobo

512 KiB

1x64 KiB

2-way set associative

write-back

wireless test

Wireless Communications

Wi-Fi

WiFi

802.11-1997	Yes
802.11a	Yes
802.11b	Yes
802.11g	Yes
802.11n	Yes
802.11ac	Yes
802.11ad	Yes

Cellular

2G

GSM

Yes

GPRS

Yes

EDGE

Yes

cdmaOne

IS-95A	Yes
IS-95B	Yes

3G

UMTS

WCDMA	Yes
HSDPA	Yes	7.2 Mbps
HSUPA	Yes	5.76 Mbps

CDMA2000

1X	Yes
1xEV-DO	Yes
1X Advanced	Yes

Satellite

mpu

AMD-X5-133ADW

General Info
Designer	AMD
Manufacturer	AMD
Model Number	AMD-X5-133ADW
Part Number	AMD-X5-133ADW, AMD-X5-133ADW, AMD-X5-133ADW
Market	Desktop
Market	Desktop

ecd9c6

comptable

Script error: The function "intel_x86" does not exist.

09/01/2015

Tabl test

Microarchitecture template

Microarchitectures
Paradigms
Single-Cycle	Multi-Cycle	Pipelining
Superpipelining	Superscalar	OOoE
Pipeline
Prefetching (instruction prefetch)
Fetching (instruction fetch)
Decoding (instruction decode)
micro-operation	macro-operation	internal operation
µOP cache	µOP fusion
Out-of-Order
OOoE	Speculative	Flushing
Components

@@ Line 89: / Line 89: @@
 == comptable ==
+{{#invoke: arch timeline|intel_x86}}
+{{#time:09/01/2015}}
 <timeline>
-ImageSize  = width:1000 height:400
+ImageSize  = width:1000 height:500
 PlotArea   = left:150 right:10 top:10 bottom:25 #left:0 right:0 bottom:20 top:0
@@ Line 133: / Line 137: @@
      bar:arch8
      bar:arch9
-   barset:Cores
+   barset:Cores1
-     bar:core1
+     bar:core11
-     bar:core2
+     bar:core12
-     bar:core3
+     bar:core13
-     bar:core4
+     bar:core14
-     bar:core5
+     bar:core15
-     bar:core6
+     bar:core16
-     bar:core7
+  barset:Cores2
-     bar:core8
+    bar:core21
-     bar:core9
+    bar:core22
+    bar:core23
+    bar:core24
+    bar:core25
+    bar:core26
+  barset:Cores3
+    bar:core31
+    bar:core32
+    bar:core33
+    bar:core34
+    bar:core35
+    bar:core36
+  barset:Cores4
+    bar:core41
+    bar:core42
+    bar:core43
+    bar:core44
+    bar:core45
+    bar:core46
+  barset:Cores5
+    bar:core51
+    bar:core52
+    bar:core53
+    bar:core54
+    bar:core55
+    bar:core56
+  barset:Cores6
+    bar:core61
+    bar:core62
+    bar:core63
+    bar:core64
+    bar:core65
+    bar:core66
+  barset:Cores7
+    bar:core71
+    bar:core72
+    bar:core73
+    bar:core74
+    bar:core75
+    bar:core76
+  barset:Cores8
+    bar:core81
+    bar:core82
+    bar:core83
+    bar:core84
+    bar:core85
+    bar:core86
+  barset:Cores9
+    bar:core91
+    bar:core92
+    bar:core93
+     bar:core94
+     bar:core95
+     bar:core96
 PlotData=
    width:22 fontsize:10 textcolor:black shift:(5,-4)
@@ Line 152: / Line 209: @@
    bar:arch6 color:c_arch6 from:08/01/2019 till:01/01/2021 anchor:from text:"[[intel/microarchitectures/tigerlake|Tigerlake]]"
-   width:15 fontsize:10
+   width:10 fontsize:10
    color:c_core1
-   bar:core1
+   bar:core11 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y"
-     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y"
+  bar:core12 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake Y"
-     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake Y"
+  bar:core13 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake Y"
-     anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake Y"
    color:c_core2
-   bar:core2
+   bar:core21 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake U"
-     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake U"
+  bar:core22 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake U"
-     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake U"
+  bar:core23 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake U"
-     anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake U"
    color:c_core3
-   bar:core3
+   bar:core31 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake H"
-     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake H"
+  bar:core32 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake H"
-     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake H"
+  bar:core33 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake H"
-     anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake H"
    color:c_core4
-   bar:core4
+   bar:core41 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake S"
-     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake S"
+  bar:core42 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake S"
-     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake S"
+  bar:core43 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake S"
-     anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake S"
    color:c_core5
-   bar:core5
+   bar:core51 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake DT"
-     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake DT"
+  bar:core52 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake DT"
-     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake DT"
+  bar:core53 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake DT"
-     anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake DT"
    color:c_core6
-   bar:core6
+   bar:core61 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake X"
-     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake X"
+  bar:core62 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake X"
-     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake X"
+  bar:core63 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake X"
-     anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake X"
    color:c_core7
-   bar:core7
+   bar:core71 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake E"
-     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake E"
+  bar:core72 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake E"
-     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake E"
+  bar:core73 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake E"
-     anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake E"
    color:c_core8
-   bar:core8
+   bar:core81 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake EP"
-     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake EP"
+  bar:core82 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake EP"
-     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake EP"
+  bar:core83 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake EP"
-     anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake EP"
    color:c_core9
-   bar:core9
+   bar:core91 anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake EX"
-     anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake EX"
+  bar:core92 anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake EX"
-     anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake EX"
+  bar:core93 anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake EX"
-     anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake EX"
 </timeline>

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Revision as of 02:51, 14 May 2017

Contents

wireless test

mpu

comptable

Tabl test

Microarchitecture template