From WikiChip
Difference between revisions of "WikiChip:sandbox"

(→‎Microarchitecture template)
(→‎comptable)
Line 94: Line 94:
  
 
DateFormat = mm/dd/yyyy
 
DateFormat = mm/dd/yyyy
−
Period    = from:2015 till:2018
+
Period    = from:2015 till:2021
 
ScaleMajor = unit:year increment:1 start:2015
 
ScaleMajor = unit:year increment:1 start:2015
 
ScaleMinor = unit:month increment:1 start:2015
 
ScaleMinor = unit:month increment:1 start:2015
Line 100: Line 100:
 
TimeAxis  = orientation:horizontal
 
TimeAxis  = orientation:horizontal
 
AlignBars  = justify
 
AlignBars  = justify
 +
 +
Colors =
 +
  id:c_arch1 value:rgb(1,0.96,0.90)
 +
  id:c_arch2 value:rgb(1,0.92,0.90)
 +
  id:c_arch3 value:rgb(1,0.88,0.80)
 +
  id:c_arch4 value:rgb(1,0.84,0.80)
 +
  id:c_arch5 value:rgb(1,0.80,0.70)
 +
  id:c_arch6 value:rgb(1,0.76,0.70)
 +
  id:c_arch7 value:rgb(1,0.72,0.60)
 +
  id:c_arch8 value:rgb(1,0.68,0.60)
 +
  id:c_arch9 value:rgb(1,0.64,0.50)
 +
 +
  id:c_core1 value:rgb(0.47,0.83,0.91)
 +
  id:c_core2 value:rgb(0.97,0.90,0.72)
 +
  id:c_core3 value:rgb(0.98,0.73,0.87)
 +
  id:c_core4 value:rgb(0.78,0.82,0.96)
 +
  id:c_core5 value:rgb(0.84,0.97,0.96)
 +
  id:c_core6 value:rgb(0.95,0.83,1)
 +
  id:c_core7 value:rgb(0.89,0.95,0.87)
 +
  id:c_core8 value:rgb(0.68,1,0.91)
 +
  id:c_core9 value:rgb(0.78,0.93,1)
  
 
BarData =
 
BarData =
 
   barset:Microarchitectures
 
   barset:Microarchitectures
−
     bar:Kaby_Lake
+
     bar:arch1
−
     bar:Skylake
+
     bar:arch2
 +
    bar:arch3
 +
    bar:arch4
 +
    bar:arch5
 +
    bar:arch6
 +
    bar:arch7
 +
    bar:arch8
 +
    bar:arch9
 
   barset:Cores
 
   barset:Cores
 +
    bar:core1
 +
    bar:core2
 +
    bar:core3
 +
    bar:core4
 +
    bar:core5
 +
    bar:core6
 +
    bar:core7
 +
    bar:core8
 +
    bar:core9
 
PlotData=
 
PlotData=
−
   bar:Kaby_Lake
+
   width:22 fontsize:10 textcolor:black shift:(5,-4)
−
    color:yelloworange width:22 fontsize:10 textcolor:black shift:(5,-4)
+
  bar:arch1 color:c_arch1 from:09/01/2015 till:01/01/2018 anchor:from text:"[[intel/microarchitectures/skylake|Skylake]]"
−
    from:08/30/2016 till:03/28/2017 anchor:from text:"[[intel/microarchitectures/kaby_lake|Kaby Lake]]"
+
  bar:arch2 color:c_arch2 from:08/30/2016 till:01/01/2019 anchor:from text:"[[intel/microarchitectures/kaby_lake|Kaby Lake]]"
−
   bar:Skylake
+
   bar:arch3 color:c_arch3 from:07/01/2017 till:01/01/2019 anchor:from text:"[[intel/microarchitectures/coffee_lake|Coffee Lake]]"
−
    color:redorange width:22 fontsize:10 textcolor:black shift:(5,-4)
+
  bar:arch4 color:c_arch4 from:10/01/2017 till:10/01/2019 anchor:from text:"[[intel/microarchitectures/cannonlake|Cannonlake]]"
−
    from:09/01/2015 till:11/10/2016 anchor:from text:"[[intel/microarchitectures/skylake|Skylake]]"
+
  bar:arch5 color:c_arch5 from:08/01/2018 till:01/01/2020 anchor:from text:"[[intel/microarchitectures/icelake|Icelake]]"
 +
  bar:arch6 color:c_arch6 from:08/01/2019 till:01/01/2021 anchor:from text:"[[intel/microarchitectures/tigerlake|Tigerlake]]"
 +
 
 +
  width:15 fontsize:10
 +
  color:c_core1
 +
  bar:core1
 +
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y"
 +
    anchor:from from:11/20/2016 till:11/09/2017 text:"Kaby Lake Y"
 +
    anchor:from from:11/12/2017 till:02/09/2019 text:"Cannonlake Y"
 +
  color:c_core2
 +
  bar:core2
 +
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y2"
 +
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U2"
 +
  color:c_core3
 +
  bar:core3
 +
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y3"
 +
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U3"
 +
  color:c_core4
 +
  bar:core4
 +
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y4"
 +
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U4"
 +
  color:c_core5
 +
  bar:core5
 +
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y5"
 +
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U5"
 +
  color:c_core6
 +
  bar:core6
 +
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y6"
 +
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U6"
 +
  color:c_core7
 +
  bar:core7
 +
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y7"
 +
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U7"
 +
  color:c_core8
 +
  bar:core8
 +
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y8"
 +
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U8"
 +
  color:c_core9
 +
  bar:core9
 +
    anchor:from from:09/05/2015 till:11/03/2016 text:"Skylake Y9"
 +
    anchor:from from:11/20/2016 till:11/09/2017 text:"Skylake U9"
 
</timeline>
 
</timeline>
 +
 +
  
 
<timeline>
 
<timeline>

Revision as of 00:34, 13 May 2017

Welcome to this sandbox page. Sandbox pages provide space to experiment with the process of editing.


 
ssssssssssss
DATA
BUS
I/O		D00116CM-RAM0X
D10215CM-RAM1X
D20314CM-RAM2X
 D30413CM-RAM3X
Vss0512VddX
CLOCK
PHASE 1/2		Ø10611CM-ROMX
Ø20710TESTX
SYNC0809RESETX
123456789


Sitemap font awesome.svgCache Info
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes.
[Edit Values]
L1$128 KiB
L1I$64 KiB1x64 KiB2-way set associativewrite-back
L1D$64 KiB1x64 KiB2-way set associativewrite-back
L2$128 KiB
L2I$64 KiB1x64 KiB2-way set associativewrite-back
L2D$64 KiB1x64 KiB2-way set associativewrite-back
L3$128 KiB
L3I$64 KiB1x64 KiB2-way set associativewrite-back
L3D$64 KiB1x64 KiB2-way set associativewrite-back
L4$128 KiB
L4I$64 KiB1x64 KiB2-way set associativewrite-back
L4D$64 KiB1x64 KiB2-way set associativewrite-back
Off-package cache support
Mobo512 KiB
1x64 KiB2-way set associativewrite-back


wireless test

Antu network-wireless-connected-100.svgWireless Communications
Wi-Fi
WiFi
802.11-1997Yes
802.11aYes
802.11bYes
802.11gYes
802.11nYes
802.11acYes
802.11adYes
Cellular
2G
GSM Yes
GPRS Yes
EDGE Yes
cdmaOne
IS-95AYes
IS-95BYes
3G
UMTS
WCDMAYes
HSDPAYes7.2 Mbps
HSUPAYes5.76 Mbps
CDMA2000
1XYes
1xEV-DOYes
1X AdvancedYes
Satellite

mpu

AMD-X5-133ADW
KL AMD 5x86.jpg
General Info
DesignerAMD
ManufacturerAMD
Model NumberAMD-X5-133ADW
Part NumberAMD-X5-133ADW,
AMD-X5-133ADW,
AMD-X5-133ADW
MarketDesktop
MarketDesktop
ecd9c6

comptable

intel/microarchitectures/tigerlakeintel/microarchitectures/icelakeintel/microarchitectures/cannonlakeintel/microarchitectures/coffee lakeintel/microarchitectures/kaby lakeintel/microarchitectures/skylake


Tabl test

Microarchitecture template

Microarchitectures
Paradigms
Single-CycleMulti-CyclePipelining
SuperpipeliningSuperscalarOOoE
Pipeline
Prefetching (instruction prefetch)
Fetching (instruction fetch)
Decoding (instruction decode)
micro-operationmacro-operationinternal operation
µOP cacheµOP fusion 
Out-of-Order
OOoESpeculativeFlushing
Components
Retrieved from "https://en.wikichip.org/w/index.php?title=WikiChip:sandbox&oldid=42675"