Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "WikiChip:sandbox"
(→Microarchitecture template) |
(→Microarchitecture template) |
||
| Line 140: | Line 140: | ||
== Microarchitecture template == | == Microarchitecture template == | ||
| − | <table style="border: solid 1px #a7d7f9; width: 375px; float: ri@@@@@ght; margin: 0 10px 10px 10px; text-align: left; font-size: 12px;"> | + | <table style="border: solid 1px #a7d7f9; width: 375px; float: ri@@@@@ght; margin: 0 10px 10px 10px; text-align: left; font-size: 12px; border-collapse: collapse;"> |
<tr><td style="text-align: center;" colspan="3">[[microarchitecture|<span style="text-decoration: none; color: #555555; text-shadow: 0px 2px 3px #222222; font-size: 20pt; font-weight: bold; ">Microarchitectures</span>]]</td></tr> | <tr><td style="text-align: center;" colspan="3">[[microarchitecture|<span style="text-decoration: none; color: #555555; text-shadow: 0px 2px 3px #222222; font-size: 20pt; font-weight: bold; ">Microarchitectures</span>]]</td></tr> | ||
<tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">'''Paradigms'''</td></tr> | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">'''Paradigms'''</td></tr> | ||
| − | <tr style="text-align: center | + | <tr style="text-align: center; "><td>[[Single-Cycle]]</td><td>[[Multi-Cycle]]</td><td>[[Pipelining]]</td></tr> |
| − | <tr style="text-align: center | + | <tr style="text-align: center; "><td>[[Superpipelining]]</td><td>[[Superscalar]]</td><td>[[OOoE]]</td></tr> |
<tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">'''Pipeline'''</td></tr> | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">'''Pipeline'''</td></tr> | ||
<tr style="text-align: center;"><td colspan="3">Prefetching ([[instruction prefetch]])</td></tr> | <tr style="text-align: center;"><td colspan="3">Prefetching ([[instruction prefetch]])</td></tr> | ||
<tr style="text-align: center;"><td colspan="3">Fetching ([[instruction fetch]])</td></tr> | <tr style="text-align: center;"><td colspan="3">Fetching ([[instruction fetch]])</td></tr> | ||
<tr style="text-align: center;"><td colspan="3">Decoding ([[instruction decode]])</td></tr> | <tr style="text-align: center;"><td colspan="3">Decoding ([[instruction decode]])</td></tr> | ||
| − | <tr style="text-align: center | + | <tr style="text-align: center; "><td>[[micro-operation]]</td><td>[[macro-operation]]</td><td>[[µOP fusion]]</td></tr> |
| − | <tr style="text-align: center | + | <tr style="text-align: center; "><td>[[µOP cache]]</td><td> </td><td> </td></tr> |
| − | + | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">'''Out-of-Order'''</td></tr> | |
| − | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">Components</td></tr> | + | <tr style="text-align: center; "><td>[[OOoE]]</td><td>[[speculative execution|Speculative]]</td><td>[[pipeline flush|Flushing]]</td></tr> |
| + | <tr style="text-align: center;"><td style="border-top: 1px solid #a7d7f9;" colspan="3">'''Components'''</td></tr> | ||
</table> | </table> | ||
Revision as of 16:47, 23 April 2017
Welcome to this sandbox page. Sandbox pages provide space to experiment with the process of editing.
| ssssssssssss | ||||||||
| DATA BUS I/O | D0 | 01 | 16 | CM-RAM0 | X | |||
| D1 | 02 | 15 | CM-RAM1 | X | ||||
| D2 | 03 | 14 | CM-RAM2 | X | ||||
| D3 | 04 | 13 | CM-RAM3 | X | ||||
| Vss | 05 | 12 | Vdd | X | ||||
| CLOCK PHASE 1/2 | Ø1 | 06 | 11 | CM-ROM | X | |||
| Ø2 | 07 | 10 | TEST | X | ||||
| SYNC | 08 | 09 | RESET | X | ||||
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
 Cache Info Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. [Edit Values]The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes. | ||||||||||||
| L1$ | 128 KiB |
| ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| L2$ | 128 KiB |
| ||||||||||
| L3$ | 128 KiB |
| ||||||||||
| L4$ | 128 KiB |
| ||||||||||
| Off-package cache support | ||||||||||||
| Mobo | 512 KiB |
| ||||||||||
wireless test
 Wireless Communications | |||||||||||||||||||
| Wi-Fi | |||||||||||||||||||
| WiFi |
| ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Cellular | |||||||||||||||||||
| 2G |
| ||||||||||||||||||
| 3G |
| ||||||||||||||||||
| Satellite | |||||||||||||||||||
mpu
| AMD-X5-133ADW | |
 | |
| General Info | |
| Designer | AMD |
|---|---|
| Manufacturer | AMD |
| Model Number | AMD-X5-133ADW |
| Part Number | AMD-X5-133ADW, AMD-X5-133ADW, AMD-X5-133ADW |
| Market | Desktop |
| Market | Desktop |
comptable
Tabl test
Microarchitecture template
| Microarchitectures | ||
| Paradigms | ||
| Single-Cycle | Multi-Cycle | Pipelining |
| Superpipelining | Superscalar | OOoE |
| Pipeline | ||
| Prefetching (instruction prefetch) | ||
| Fetching (instruction fetch) | ||
| Decoding (instruction decode) | ||
| micro-operation | macro-operation | µOP fusion |
| µOP cache | ||
| Out-of-Order | ||
| OOoE | Speculative | Flushing |
| Components | ||
