Semiconductor & Computer Engineering
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Difference between revisions of "wall"
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| − | A '''wall''' refers to a point (i.e., a physical limitation) in which a certain aspect of an [[integrated circuit]] cannot be exceeded without experiencing a large diminishing return or even adverse effects. While most closely associated with [[microprocessor]]s and [[CPU]]s, the term applies equally to all integrated circuits. | + | A '''wall''' refers to a point (i.e., a physical limitation) in which a certain aspect of an [[integrated circuit]] cannot be exceeded without experiencing a large diminishing return or even adverse effects. While most closely associated with [[microprocessor]]s and [[CPU]]s, the term applies equally to all integrated circuits. |
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| + | Mainstream consumer products continue to demand higher level of computational power. As performance goals continued to drive the design of [[microprocessor]]s, many aspects are pushed to higher with the expectation that performance will continue to scale linearly with them; this is largely due to misformulation of [[Moore's Law]]. | ||
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| + | == Types of walls == | ||
| + | * '''[[Memory Wall]]''' - Latency induced bandwidth limitations; a growing disparity of speed between the CPU and memory | ||
| + | * '''[[Power Wall]]''' - Exponential increase in power as frequency is scaled | ||
| + | * '''[[Frequency Wall]]''' - Diminishing returns from deeper pipelines | ||
| + | * '''[[ILP Wall]]''' - Exceedingly difficult to extract enough parallelism, coupled with speculative execution and data dependencies | ||
Revision as of 18:01, 21 March 2017
A wall refers to a point (i.e., a physical limitation) in which a certain aspect of an integrated circuit cannot be exceeded without experiencing a large diminishing return or even adverse effects. While most closely associated with microprocessors and CPUs, the term applies equally to all integrated circuits.
Mainstream consumer products continue to demand higher level of computational power. As performance goals continued to drive the design of microprocessors, many aspects are pushed to higher with the expectation that performance will continue to scale linearly with them; this is largely due to misformulation of Moore's Law.
Types of walls
- Memory Wall - Latency induced bandwidth limitations; a growing disparity of speed between the CPU and memory
- Power Wall - Exponential increase in power as frequency is scaled
- Frequency Wall - Diminishing returns from deeper pipelines
- ILP Wall - Exceedingly difficult to extract enough parallelism, coupled with speculative execution and data dependencies