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Difference between revisions of "loongson/godson 2/2d1"
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'''Godson-2D1''' ('''龙芯2D1''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers.The Godson-2D1 operates at up to 800 MHz consuming 3-5W. This chip was manufactured on [[STMicroelectronics]]' [[0.13 µm process]]. This chip reached tapeout on January 6, 2005.
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'''Godson-2D1''' ('''龙芯2D1''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers.The Godson-2D1 operates at up to 800 MHz consuming up to 6 W. This chip was manufactured on [[STMicroelectronics]]' [[0.13 µm process]]. This chip reached tapeout on January 6, 2005.
  
 
Loongson has claimed the Godson-2D has reached the performance level of 1.5 GHz {{intel|PIV}} based on their SPECint2000 scores.
 
Loongson has claimed the Godson-2D has reached the performance level of 1.5 GHz {{intel|PIV}} based on their SPECint2000 scores.

Revision as of 20:59, 19 March 2017

Template:mpu Godson-2D1 (龙芯2D1) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers.The Godson-2D1 operates at up to 800 MHz consuming up to 6 W. This chip was manufactured on STMicroelectronics' 0.13 µm process. This chip reached tapeout on January 6, 2005.

Loongson has claimed the Godson-2D has reached the performance level of 1.5 GHz PIV based on their SPECint2000 scores.

Cache

Main article: GS464 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
Facts about "Godson-2D1 - Loongson"
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +