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| package module 1 = {{packages/amd/socket am4}} | | package module 1 = {{packages/amd/socket am4}} | ||
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− | '''Ryzen 5 1500X''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] desktop microprocessor set to be introduced by [[AMD]] in early [[2017]]. This processor is based on AMD's {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[14 nm process]]. The 1500X operates at a base frequency of 3.5 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of 3.8 GHz. This MPU supports up to 64 GiB of dual-channel | + | '''Ryzen 5 1500X''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] desktop microprocessor set to be introduced by [[AMD]] in early [[2017]]. This processor is based on AMD's {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[14 nm process]]. The 1500X operates at a base frequency of 3.5 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of 3.8 GHz. This MPU supports up to 64 GiB of dual-channel DDR4-2400 ECC memory. |
== Cache == | == Cache == | ||
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== Memory controller == | == Memory controller == | ||
+ | While officially supporting up to DDR4-2400, this processor can support much higher frequencies (3200 or even higher have been observed) with proper motherboard support. Additionally, while not officially supported, this processor also has [[ECC]] memory support. | ||
{{memory controller | {{memory controller | ||
|type=DDR4-2400 | |type=DDR4-2400 | ||
− | |ecc= | + | |ecc=Yes |
|max mem=64 GiB | |max mem=64 GiB | ||
|controllers=1 | |controllers=1 |
Revision as of 03:28, 3 March 2017
Template:mpu Ryzen 5 1500X is a 64-bit quad-core mid-range performance x86 desktop microprocessor set to be introduced by AMD in early 2017. This processor is based on AMD's Zen microarchitecture and is fabricated on a 14 nm process. The 1500X operates at a base frequency of 3.5 GHz with a TDP of 65 W and a Boost frequency of 3.8 GHz. This MPU supports up to 64 GiB of dual-channel DDR4-2400 ECC memory.
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
While officially supporting up to DDR4-2400, this processor can support much higher frequencies (3200 or even higher have been observed) with proper motherboard support. Additionally, while not officially supported, this processor also has ECC memory support.
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
This processor has no integrated graphics.
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Shop
<amazon type="simple-listing1" search-title="AMD Ryzen" search-phrase="AMD Ryzen" />
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Ryzen 5 1500X - AMD#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd extended frequency range | true + |
has amd sensemi technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Extended Frequency Range + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 20 + |
supported memory type | DDR4-2400 + |