Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i5/i5-7442eq"
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|bandwidth schan=15.89 GiB/s | |bandwidth schan=15.89 GiB/s | ||
|bandwidth dchan=31.79 GiB/s | |bandwidth dchan=31.79 GiB/s | ||
| + | }} | ||
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| + | == Expansions == | ||
| + | {{expansions | ||
| + | | pcie revision = 3.0 | ||
| + | | pcie lanes = 16 | ||
| + | | pcie config = 1x16 | ||
| + | | pcie config 2 = 2x8 | ||
| + | | pcie config 3 = 1x8+2x4 | ||
}} | }} | ||
Revision as of 19:27, 6 January 2017
Template:mpu Core i5-7442EQ is a 64-bit quad-core mid-range performance x86 embedded microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The i5-7442EQ operates at 2.1 GHz with a TDP of 25 W supporting a Turbo Boost frequency of 2.9 GHz. The processor supports up to 64 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with a burst frequency of 1 GHz.
Cache
- Main article: Kaby Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Facts about "Core i5-7442EQ - Intel"
| has ecc memory support | false + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 12-way set associative + |
| l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
| max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
| max memory channels | 2 + |
| supported memory type | DDR3L-1600 + and DDR4-2133 + |