From WikiChip
Difference between revisions of "intel/core i5/i5-7y54"
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== Graphics == | == Graphics == | ||
− | {{integrated | + | {{integrated graphics |
− | | gpu = | + | | gpu = HD Graphics 615 |
| device id = 0x591E | | device id = 0x591E | ||
+ | | designer = Intel | ||
| execution units = 24 | | execution units = 24 | ||
− | | displays | + | | max displays = 3 |
+ | | max memory = 16 GiB | ||
| frequency = 300 MHz | | frequency = 300 MHz | ||
| max frequency = 950 MHz | | max frequency = 950 MHz | ||
− | |||
| output crt = | | output crt = | ||
Line 155: | Line 156: | ||
| output dvi = Yes | | output dvi = Yes | ||
− | | directx ver | + | | directx ver = 12 |
− | | opengl ver | + | | opengl ver = 4.4 |
− | | opencl ver | + | | opencl ver = 2.0 |
− | | | + | | hdmi ver = 1.4a |
− | | | + | | dp ver = 1.2 |
− | | | + | | edp ver = 1.3 |
− | | | + | | max res hdmi = 4096x2304 |
− | | | + | | max res hdmi freq = 24 Hz |
− | | dp | + | | max res dp = 4096x2304 |
− | | edp | + | | max res dp freq = 60 Hz |
+ | | max res edp = 4096x2304 | ||
+ | | max res edp freq = 60 Hz | ||
+ | | max res vga = | ||
+ | | max res vga freq = | ||
− | | | + | | features = Yes |
− | + | | intel quick sync = Yes | |
− | + | | intel intru 3d = Yes | |
− | + | | intel insider = | |
− | + | | intel widi = | |
− | + | | intel fdi = | |
− | + | | intel clear video = Yes | |
− | + | | intel clear video hd = Yes | |
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− | | intel quick sync | ||
− | | intel intru 3d | ||
− | | intel insider | ||
− | | intel widi | ||
− | | intel fdi | ||
− | | intel clear video | ||
}} | }} | ||
Revision as of 17:56, 6 January 2017
Template:mpu Core i5-7Y54 is a 64-bit dual-core mid-range performance x86 mobile microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The i5-7Y54 operates at 1.2 GHz with a TDP of 4.5 W supporting a Turbo Boost frequency of 3.2 GHz. The processor supports up to 16 GiB of dual-channel non-ECC LPDDR3-1866 memory and incorporates Intel's HD Graphics 615 IGP operating at 300 MHz with a burst frequency of 950 MHz.
Cache
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
Integrated Graphics Information
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Features
Facts about "Core i5-7Y54 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-7Y54 - Intel#io + |
device id | 0x591E + |
has ecc memory support | false + |
integrated gpu | HD Graphics 615 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 950 MHz (0.95 GHz, 950,000 KHz) + |
integrated gpu max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
max memory bandwidth | 27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 10 + |
supported memory type | DDR3L-1600 + and LPDDR3-1866 + |