From WikiChip
Difference between revisions of "intel/core i5/i5-7300u"
< intel‎ | core i5

(+memory controller)
(+expansions)
Line 122: Line 122:
 
|bandwidth schan=15.89 GiB/s
 
|bandwidth schan=15.89 GiB/s
 
|bandwidth dchan=31.79 GiB/s
 
|bandwidth dchan=31.79 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 12
 +
| pcie config        = 1x4
 +
| pcie config 2      = 2x2
 +
| pcie config 3      = 1x2+2x1
 +
| pcie config 4      = 4x1
 
}}
 
}}

Revision as of 17:46, 6 January 2017

Template:mpu Core i5-7300U is a 64-bit dual-core mid-range performance x86 mobile microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The i5-7300U operates at 2.6 GHz with a TDP of 15 W supporting a Turbo Boost frequency of 3.5 GHz. The processor supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's HD Graphics 620 IGP operating at 300 MHz with a burst frequency of 1.1 GHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back

L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back

L3$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
  2x1.5 MiB12-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866, DDR3L-1600, DDR4-2133
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes12
Configs1x4, 2x2, 1x2+2x1, 4x1
Facts about "Core i5-7300U - Intel"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core i5-7300U - Intel#io +
has ecc memory supportfalse +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description12-way set associative +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes12 +
supported memory typeLPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 +