From WikiChip
Difference between revisions of "intel/core i5/i5-7500"
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== Graphics == | == Graphics == | ||
− | {{integrated | + | {{integrated graphics |
− | | gpu = | + | | gpu = HD Graphics 630 |
− | | device id = | + | | device id = 0x5912 |
+ | | designer = Intel | ||
| execution units = 24 | | execution units = 24 | ||
− | | displays | + | | max displays = 3 |
− | | frequency = | + | | max memory = 64 GiB |
− | | max frequency = | + | | frequency = 350 MHz |
− | + | | max frequency = 1,100 MHz | |
| output crt = | | output crt = | ||
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| output dvi = Yes | | output dvi = Yes | ||
− | | directx ver | + | | directx ver = 12 |
− | | opengl ver | + | | opengl ver = 4.4 |
− | | opencl ver | + | | opencl ver = 2.0 |
− | | | + | | hdmi ver = 1.4a |
− | | | + | | dp ver = 1.2 |
− | | | + | | edp ver = 1.3 |
− | | | + | | max res hdmi = 4096x2304 |
− | | | + | | max res hdmi freq = 24 Hz |
− | | dp | + | | max res dp = 4096x2304 |
− | | edp | + | | max res dp freq = 60 Hz |
+ | | max res edp = 4096x2304 | ||
+ | | max res edp freq = 60 Hz | ||
+ | | max res vga = | ||
+ | | max res vga freq = | ||
− | | | + | | features = Yes |
− | + | | intel quick sync = Yes | |
− | + | | intel intru 3d = Yes | |
− | + | | intel insider = | |
− | + | | intel widi = | |
− | + | | intel fdi = | |
− | + | | intel clear video = Yes | |
− | + | | intel clear video hd = Yes | |
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Revision as of 17:09, 6 January 2017
Template:mpu Core i5-7500 is a 64-bit quad-core mid-range performance x86 microprocessor introduced by Intel in early 2017 for the desktop and embedded markets. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The i5-7500 operates at 3.4 GHz with a TDP of 65 W supporting a Turbo Boost frequency of 3.8 GHz. The processor supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory and incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with a burst frequency of 1.1 GHz.
Cache
- Main article: Kaby Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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Features
Facts about "Core i5-7500 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-7500 - Intel#io + |
device id | 0x5912 + |
has ecc memory support | false + |
integrated gpu | HD Graphics 630 + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 1,100 MHz (1.1 GHz, 1,100,000 KHz) + |
integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | DDR3L-1600 + and DDR4-2400 + |