From WikiChip
Difference between revisions of "intel/core i5/i5-7442eq"
< intel‎ | core i5

(+cache info)
Line 88: Line 88:
 
}}
 
}}
 
'''Core i5-7442EQ''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile embedded microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The i5-7442EQ operates at 2.1 GHz with a TDP of 25 W supporting a {{intel|Turbo Boost}} frequency of 2.9 GHz. The processor supports up to 64 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's {{intel|HD Graphics 630}} [[IGP]] operating at 350 MHz with a burst frequency of 1 GHz.
 
'''Core i5-7442EQ''' is a {{arch|64}} [[quad-core]] mid-range performance [[x86]] mobile embedded microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The i5-7442EQ operates at 2.1 GHz with a TDP of 25 W supporting a {{intel|Turbo Boost}} frequency of 2.9 GHz. The processor supports up to 64 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's {{intel|HD Graphics 630}} [[IGP]] operating at 350 MHz with a burst frequency of 1 GHz.
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i policy=write-back
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=1 MiB
 +
|l2 break=4x256 KiB
 +
|l2 desc=4-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=6 MiB
 +
|l3 break=4x1.5 MiB
 +
|l3 desc=12-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 05:51, 6 January 2017

Template:mpu Core i5-7442EQ is a 64-bit quad-core mid-range performance x86 mobile embedded microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The i5-7442EQ operates at 2.1 GHz with a TDP of 25 W supporting a Turbo Boost frequency of 2.9 GHz. The processor supports up to 64 GiB of dual-channel non-ECC DDR4-2133 memory and incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with a burst frequency of 1 GHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  4x1.5 MiB12-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i5/i5-7442eq&oldid=33051"
Facts about "Core i5-7442EQ - Intel"
RDF feed
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description12-way set associative +
l3$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +