From WikiChip
Difference between revisions of "intel/core i5/i5-7y57"
< intel‎ | core i5

(+cache info)
Line 90: Line 90:
 
}}
 
}}
 
'''Core i5-7Y57''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The i5-7Y57 operates at 1.2 GHz with a TDP of 4.5 W supporting a {{intel|Turbo Boost}} frequency of 3.3 GHz. The processor supports up to 16 GiB of dual-channel non-ECC LPDDR3-1866 memory and incorporates Intel's {{intel|HD Graphics 615}} [[IGP]] operating at 300 MHz with a burst frequency of 950 MHz.
 
'''Core i5-7Y57''' is a {{arch|64}} [[dual-core]] mid-range performance [[x86]] mobile microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The i5-7Y57 operates at 1.2 GHz with a TDP of 4.5 W supporting a {{intel|Turbo Boost}} frequency of 3.3 GHz. The processor supports up to 16 GiB of dual-channel non-ECC LPDDR3-1866 memory and incorporates Intel's {{intel|HD Graphics 615}} [[IGP]] operating at 300 MHz with a burst frequency of 950 MHz.
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
 +
{{cache size
 +
|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=2x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i policy=write-back
 +
|l1d cache=64 KiB
 +
|l1d break=2x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=512 KiB
 +
|l2 break=2x256 KiB
 +
|l2 desc=4-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=4 MiB
 +
|l3 break=2x2 MiB
 +
|l3 desc=12-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 05:45, 6 January 2017

Template:mpu Core i5-7Y57 is a 64-bit dual-core mid-range performance x86 mobile microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The i5-7Y57 operates at 1.2 GHz with a TDP of 4.5 W supporting a Turbo Boost frequency of 3.3 GHz. The processor supports up to 16 GiB of dual-channel non-ECC LPDDR3-1866 memory and incorporates Intel's HD Graphics 615 IGP operating at 300 MHz with a burst frequency of 950 MHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  2x2 MiB12-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i5/i5-7y57&oldid=33042"
Facts about "Core i5-7Y57 - Intel"
RDF feed
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description12-way set associative +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +