From WikiChip
Difference between revisions of "intel/core i5/i5-7400"
< intel‎ | core i5

Line 1: Line 1:
 
{{intel title|Core i5-7400}}
 
{{intel title|Core i5-7400}}
 
{{mpu
 
{{mpu
−
| future              = Yes
 
 
| name                = Core i5-7400
 
| name                = Core i5-7400
−
| no image            = yes
+
| no image            = Yes
 
| image              =  
 
| image              =  
 
| image size          =  
 
| image size          =  
Line 10: Line 9:
 
| manufacturer        = Intel
 
| manufacturer        = Intel
 
| model number        = i5-7400
 
| model number        = i5-7400
−
| part number        = BX80677I57400
+
| part number        = CM8067702867050
−
| part number 1      = CM8067702867050
+
| part number 1      = BXC80677I57400
−
| part number 2      =  
+
| part number 2      = BX80677I57400
−
| part number 3      =  
+
| s-spec              = SR32W
 
| market              = Desktop
 
| market              = Desktop
−
| first announced    = October 28, 2016
+
| first announced    = January 3, 2017
−
| first launched      = 2017
+
| first launched      = January 3, 2017
 
| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
−
| release price      = $189.00
+
| release price      = $182.00
  
 
| family              = Core i5
 
| family              = Core i5
−
| series              =  
+
| series              = i5-7400
 
| locked              = Yes
 
| locked              = Yes
 
| frequency          = 3,000 MHz
 
| frequency          = 3,000 MHz
−
| turbo frequency    =  
+
| turbo frequency    = Yes
−
| turbo frequency1    =  
+
| turbo frequency1    = 3,500 MHz
 
| turbo frequency2    =  
 
| turbo frequency2    =  
 
| turbo frequency3    =  
 
| turbo frequency3    =  
 
| turbo frequency4    =  
 
| turbo frequency4    =  
−
| turbo frequency5    =
 
−
| turbo frequency6    =
 
−
| turbo frequency7    =
 
−
| turbo frequency8    =
 
 
| bus type            = DMI 3.0
 
| bus type            = DMI 3.0
 
| bus speed          =  
 
| bus speed          =  
 
| bus rate            = 8 GT/s
 
| bus rate            = 8 GT/s
 +
| bus links          =
 
| clock multiplier    = 30
 
| clock multiplier    = 30
−
| s-spec              = SR32W
 
−
| s-spec es          =
 
−
| s-spec qs          = QKZQ
 
 
| cpuid              =  
 
| cpuid              =  
  
 +
| isa family          = x86
 +
| isa                = x86-64
 
| microarch          = Kaby Lake
 
| microarch          = Kaby Lake
−
| platform            =  
+
| platform            = Kaby Lake
−
| chipset            =  
+
| chipset            = Sunrise Point
 +
| chipset 2          = Union Point
 
| core name          = Kaby Lake S
 
| core name          = Kaby Lake S
 
| core family        = 6
 
| core family        = 6
−
| core model          =  
+
| core model          = 158
 
| core stepping      = B0
 
| core stepping      = B0
 +
| core stepping 2    =
 
| process            = 14 nm
 
| process            = 14 nm
 
| transistors        =  
 
| transistors        =  
Line 56: Line 53:
 
| die width          =  
 
| die width          =  
 
| die length          =  
 
| die length          =  
−
| word size          = 32 bit
+
| word size          = 64 bit
 
| core count          = 4
 
| core count          = 4
 
| thread count        = 4
 
| thread count        = 4
 
| max cpus            = 1
 
| max cpus            = 1
−
| max memory          = 64 GB
+
| max memory          = 64 GiB
−
| max memory addr    =
 
  
 
| electrical          = Yes
 
| electrical          = Yes
−
| power              =
+
| v core min          = 0.55 V
−
| v core             =  
+
| v core max          = 1.52 V
−
| v core tolerance    =
 
−
| v io                =
 
−
| v io tolerance      =  
 
 
| sdp                =  
 
| sdp                =  
 
| tdp                = 65 W
 
| tdp                = 65 W
−
| temp min            =  
+
| tdp typical        =
−
| temp max            =  
+
| ctdp down          =
−
| tjunc min          =  
+
| ctdp down frequency =
−
| tjunc max          =  
+
| ctdp up            =  
−
| tcase min          = 0 °C
+
| ctdp up frequency  =  
−
| tcase max          = 66 °C
+
| tjunc min          = 0 °C
−
| tstorage min        =  
+
| tjunc max          = 100 °C
−
| tstorage max        =  
+
| tcase min          =  
 +
| tcase max          =  
 +
| tstorage min        = -25 °C
 +
| tstorage max        = 125 °C
 +
| tambient min        =  
 +
| tambient max        =  
  
−
| packaging          = Yes
+
| package module 1    = {{packages/intel/lga-1151}}
−
| package             = FCLGA-1151
 
−
| package type        = FCLGA
 
−
| package pitch      = 0.914 mm
 
−
| package size        = 37.5 mm x 37.5 mm
 
−
| socket              = LGA-1151
 
−
| socket type        = LGA
 
 
}}
 
}}
 
The '''Core i5-7400''' is a {{arch|64}} [[x86]] [[quad-core microprocessor]] based on {{intel|Kaby Lake|l=arch}} and is set to be introduced by [[Intel]] in late 2016 or early 2017. This MPU operates at 3 GHz with a TDP of 65 W.
 
The '''Core i5-7400''' is a {{arch|64}} [[x86]] [[quad-core microprocessor]] based on {{intel|Kaby Lake|l=arch}} and is set to be introduced by [[Intel]] in late 2016 or early 2017. This MPU operates at 3 GHz with a TDP of 65 W.

Revision as of 03:37, 6 January 2017

Template:mpu The Core i5-7400 is a 64-bit x86 quad-core microprocessor based on Kaby Lake and is set to be introduced by Intel in late 2016 or early 2017. This MPU operates at 3 GHz with a TDP of 65 W.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Kaby Lake § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 4-way set associative (per core, write-back)
L3$ 6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
shared

Graphics

Integrated Graphic Information
GPU Intel HD Graphics 630
Execution Units 24
Displays 3
Frequency  ? MHz
"? MHz" is not a number.
Max frequency  ? GHz
"? GHz" is not a number.
Max memory 64 GB
"GB" is not declared as a valid unit of measurement for this property.
Output DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX 12.1
OpenGL 4.4
OpenCL 2.0
HDMI 1.4
DP 1.2
eDP 1.3
Max HDMI Res 4096x2304 @24 Hz
Max DP Res 4096x2304 @60 Hz
Max eDP Res 4096x2304 @60 Hz
Intel Quick Sync Video
Intel InTru 3D
Intel Insider
Intel WiDi (Wireless Display)
Intel Clear Video

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR4-1866, DDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max bandwidth 34.1 GB/s
Max memory 64 GB

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i5/i5-7400&oldid=32996"
Facts about "Core i5-7400 - Intel"
RDF feed
has featureintegrated gpu +
integrated gpuIntel HD Graphics 630 +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ descriptionshared +
l3$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +