From WikiChip
Difference between revisions of "intel/celeron/3865u"
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| pcie config 2 = 2x8 | | pcie config 2 = 2x8 | ||
| pcie config 3 = 1x8+2x4 | | pcie config 3 = 1x8+2x4 | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | {{integrated graphics | ||
+ | | gpu = HD Graphics 610 | ||
+ | | device id = 0x5906 | ||
+ | | designer = Intel | ||
+ | | execution units = 12 | ||
+ | | max displays = 3 | ||
+ | | max memory = 64 GiB | ||
+ | | frequency = 350 MHz | ||
+ | | max frequency = 900 MHz | ||
+ | |||
+ | | output crt = | ||
+ | | output sdvo = | ||
+ | | output dsi = | ||
+ | | output edp = Yes | ||
+ | | output dp = Yes | ||
+ | | output hdmi = Yes | ||
+ | | output vga = | ||
+ | | output dvi = Yes | ||
+ | |||
+ | | directx ver = 12 | ||
+ | | opengl ver = 4.4 | ||
+ | | opencl ver = 2.0 | ||
+ | | hdmi ver = 1.4a | ||
+ | | dp ver = 1.2 | ||
+ | | edp ver = 1.3 | ||
+ | | max res hdmi = 4096x2304 | ||
+ | | max res hdmi freq = 24 Hz | ||
+ | | max res dp = 4096x2304 | ||
+ | | max res dp freq = 60 Hz | ||
+ | | max res edp = 4096x2304 | ||
+ | | max res edp freq = 60 Hz | ||
+ | | max res vga = | ||
+ | | max res vga freq = | ||
+ | |||
+ | | features = Yes | ||
+ | | intel quick sync = Yes | ||
+ | | intel intru 3d = | ||
+ | | intel insider = | ||
+ | | intel widi = | ||
+ | | intel fdi = | ||
+ | | intel clear video = Yes | ||
+ | | intel clear video hd = Yes | ||
}} | }} |
Revision as of 17:55, 5 January 2017
Template:mpu Celeron 3865U is a 64-bit dual-core budget x86 mobile microprocessors introduced by Intel in early 2017. The 3865U, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 1.8 GHz and with a TDP of 15 W and supports up to 32 GiB of dual-channel non-ECC DDR4-2133. Additionally the 3865U incorporates Intel's HD Graphics 610 IGP operating at 300 MHz with a burst frequency of 900 GHz.
Contents
Cache
- Main article: Kaby Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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Facts about "Celeron 3865U - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron 3865U - Intel#io + |
device id | 0x5906 + |
has ecc memory support | false + |
integrated gpu | HD Graphics 610 + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |