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Difference between revisions of "intel/core i3/i3-7300t"
< intel‎ | core i3

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This specific model has a configurable TDP-down frequency of 2.50 GHz.
 
This specific model has a configurable TDP-down frequency of 2.50 GHz.
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== Cache ==
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{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
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{{cache size
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|l1 cache=128 KiB
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|l1i cache=64 KiB
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|l1i break=2x32 KiB
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|l1i desc=8-way set associative
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|l1i policy=write-back
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|l1d cache=64 KiB
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|l1d break=2x32 KiB
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|l1d desc=8-way set associative
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|l1d policy=write-back
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|l2 cache=512 KiB
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|l2 break=2x256 KiB
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|l2 desc=4-way set associative
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|l2 policy=write-back
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|l3 cache=4 MiB
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|l3 break=2x2 MiB
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|l3 desc=16-way set associative
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|l3 policy=write-back
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}}

Revision as of 18:44, 4 January 2017

Template:mpu Core i3-7300T is a 64-bit dual-core low-end performance x86 desktop microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14 nm+ process. This processor, which has a base frequency of 3.5 GHz with a TDP of 35 Watts, supports up to 64 GiB of dual-channel DDR4-2400. The i3-7300T incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with burst frequency of 1.10 GHz.

This specific model has a configurable TDP-down frequency of 2.50 GHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB4-way set associativewrite-back
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  2x2 MiB16-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-7300t&oldid=32599"
Facts about "Core i3-7300T - Intel"
RDF feed
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description16-way set associative +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +