Semiconductor & Computer Engineering
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Difference between revisions of "cavium/octeon plus/cn5745-800bg1217-sp"
(Created page with "{{cavium title|CN5745-800 SP}} {{mpu | name = Cavium CN5745-800 SP | no image = | image = Octeon CN57xx.svg | image size = |...") |
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| package 0 pins = 1217 | | package 0 pins = 1217 | ||
| package 0 pitch = | | package 0 pitch = | ||
| − | | package 0 width = | + | | package 0 width = 40 mm |
| − | | package 0 length = | + | | package 0 length = 40 mm |
| package 0 height = | | package 0 height = | ||
| socket 0 = BGA-1217 | | socket 0 = BGA-1217 | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
}} | }} | ||
| + | '''CN5745-800 SP''' is a {{arch|64}} [[deca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates ten {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration. | ||
Revision as of 00:33, 29 December 2016
Template:mpu CN5745-800 SP is a 64-bit deca-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates ten cnMIPS cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.
Facts about "CN5745-800 SP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5745-800 SP - Cavium#io + |
| has ecc memory support | true + |
| has hardware accelerators for data compression | true + |
| has hardware accelerators for data decompression | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| has hardware raid 5 support | true + |
| has hardware raid 6 support | true + |
| l1$ size | 480 KiB (491,520 B, 0.469 MiB) + |
| l1d$ size | 160 KiB (163,840 B, 0.156 MiB) + |
| l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 8 + |
| supported memory type | DDR2-800 + |